专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明专利

DE202021104173U1 Solarenergie-betriebenes Smart Helm-Gerät 未知
公开(公告)号：DE202021104173U1
公开(公告)日：2021-08-12
申请号：DE202021104173
申请日：2021-08-05
申请人： ALADIYAN AMBIKAPATHY , DHARMASA POOJA , GUNASEKARAN KANIMOZHI , KUMAR ASHWANI , KUMAR DILIP , KUMAR NAGENDRA , KUMAR VARUN , KUPPUSAMY SAMPATH KUMAR , SINGH AKHILESH , SRIVASTAVA ANKIT KUMAR , THANGAMARIAPPAN GANESH KUMAR
IPC分类号： A42B3/26
摘要： Ein mit Solarenergie betriebenes intelligentes Helmgerät, das Gerät umfasst:einen Helmkörper, der am Kopf eines Trägers getragen wird, wobei der Helmkörper eine Rückenseite und eine Bauchseite aufweist, wobei ein Solarpanel auf der Rückenseite maskiert ist, um elektrische Energie bereitzustellen;mindestens zwei Gebläse, die mit mindestens zwei Belüftungsöffnungen in Eingriff stehen, die an Verbindungsenden eines Visiers des Helms zum Reinigen von Wasser, Nebel und Staubpartikeln, die sich beim Regen oder Fahren auf dem Visier angesammelt haben, hergestellt sind;einen an der ventralen Seite angeordneten Airbag, der konfiguriert ist, um während des freien Falls oder sofortigen Aufpralls des Fahrrads oder Helms aktiviert zu werden, um den Kopf eines Benutzers vor einem Unfall zu schützen; undeine Steuereinheit, die mit dem Helmkörper und der Zündkerze des Fahrrads verbunden ist, um ein Starten des Fahrrads zu verhindern, wenn der Helmkörper von dem Benutzer nicht getragen wird, wobei die Steuereinheit von dem Solarpanel mit Strom versorgt wird.

2. 发明申请

WO2012115880A8 DELAY CELL FOR CLOCK SIGNALS 审中-公开
标题翻译：延迟信号用于时钟信号
公开(公告)号：WO2012115880A8
公开(公告)日：2013-08-29
申请号：PCT/US2012025695
申请日：2012-02-17
申请人： QUALCOMM INC , QUAN XIAOHONG , SRIVASTAVA ANKIT
发明人： QUAN XIAOHONG , SRIVASTAVA ANKIT
IPC分类号： H03K5/13
CPC分类号： H03K5/133 , H03L7/16
摘要： An integrated circuit for delaying a clock signal using a delay cell is described. The integrated circuit includes a current starved inverter. The current starved inverter includes a switched capacitor current source with a first dummy inverter, a first amplifier coupled to the first dummy inverter and a first capacitor coupled to the first amplifier via a first switch. The current starved inverter also includes a first transistor coupled to the current source. The integrated circuit also includes a second capacitor. A delay applied to the clock signal is dependent on a ratio between the first capacitor and the second capacitor. The first capacitor and the second capacitor may be located in proximity such that process, voltage and temperature variations affect the first capacitor and the second capacitor similarly and the delay applied to the clock signal is independent of process, voltage and temperature variations
摘要翻译：描述了使用延迟单元来延迟时钟信号的集成电路。集成电路包括电流欠压逆变器。目前的饥饿逆变器包括具有第一虚拟逆变器的开关电容器电流源，耦合到第一虚拟反相器的第一放大器和经由第一开关耦合到第一放大器的第一电容器。目前的饥饿逆变器还包括耦合到电流源的第一晶体管。集成电路还包括第二电容器。施加到时钟信号的延迟取决于第一电容器和第二电容器之间的比率。第一电容器和第二电容器可以位于接近处，使得过程，电压和温度变化类似地影响第一电容器和第二电容器，并且施加到时钟信号的延迟与过程，电压和温度变化无关

3. 发明申请

WO2023004570A1 ACTIVATION BUFFER ARCHITECTURE FOR DATA-REUSE IN A NEURAL NETWORK ACCELERATOR 审中-公开
公开(公告)号：WO2023004570A1
公开(公告)日：2023-02-02
申请号：PCT/CN2021/108594
申请日：2021-07-27
申请人： QUALCOMM INCORPORATED , WADHWA, Sameer , MOHAN, Suren , ZHU, Peiyu , LI, Ren , SRIVASTAVA, Ankit , MIRHAJ, Seyed Arash
发明人： WADHWA, Sameer , MOHAN, Suren , ZHU, Peiyu , LI, Ren , SRIVASTAVA, Ankit , MIRHAJ, Seyed Arash
IPC分类号： G06N3/04 , G06N3/063
摘要： Certain aspects provide an apparatus for signal processing in a neural network. The apparatus generally includes computation circuitry configured to perform a convolution operation, the computation circuitry having multiple input rows, and an activation buffer having multiple buffer segments coupled to the multiple input rows of the computation circuitry, respectively. In some aspects, each of the multiple buffer segments comprises a first multiplexer having a plurality of multiplexer inputs, and each of the plurality of multiplexer inputs of one of the first multiplexers on one of the multiple buffer segments is coupled to a data output of the activation buffer on another one of the multiple buffer segments.

4. 发明申请

WO2013026065A1 A SUPPLY COLLAPSE DETECTION CIRCUIT 审中-公开
标题翻译：电源检测电路
公开(公告)号：WO2013026065A1
公开(公告)日：2013-02-21
申请号：PCT/US2012/051621
申请日：2012-08-20
申请人： QUALCOMM INCORPORATED , SRIVASTAVA, Ankit
发明人： SRIVASTAVA, Ankit
IPC分类号： G06F1/30 , H03K19/00
CPC分类号： G06F1/28 , H03K19/0013
摘要： A supply collapse detection circuit is described. The supply collapse detection circuit includes threshold detection circuitry coupled to a first power supply and to a second power supply that provides a second voltage. The supply collapse detection circuit also includes supply collapse output circuitry coupled to the threshold detection circuitry to receive a detection signal when the second voltage drops. The supply collapse output circuitry includes an output node to provide an output signal indicating the drop. The supply collapse detection circuit additionally includes feedback circuitry coupled to the first power supply, to the threshold detection circuitry and to the supply collapse output circuitry. The feedback circuitry reduces leakage when the second voltage drops.
摘要翻译：描述电源塌陷检测电路。电源崩溃检测电路包括耦合到第一电源的阈值检测电路和提供第二电压的第二电源。供应塌陷检测电路还包括耦合到阈值检测电路的电源塌陷输出电路，以在第二电压下降时接收检测信号。电源崩溃输出电路包括一个输出节点，用于提供一个指示下降的输出信号。供应崩溃检测电路另外包括耦合到第一电源的反馈电路，阈值检测电路和电源崩溃输出电路。当第二电压下降时，反馈电路减少泄漏。

5. 发明申请

WO2012125766A3 CHARGE PUMP SURGE CURRENT REDUCTION 审中-公开
公开(公告)号：WO2012125766A3
公开(公告)日：2012-09-20
申请号：PCT/US2012/029128
申请日：2012-03-14
申请人： QUALCOMM INCORPORATED , QUAN, Xiaohong , SRIVASTAVA, Ankit , MIAO, Guoqing
发明人： QUAN, Xiaohong , SRIVASTAVA, Ankit , MIAO, Guoqing
IPC分类号： H02M3/07
摘要： Techniques for reducing surge current in charge pumps. In an exemplary embodiment, one or more switches coupling a terminal of a flying capacitor to a voltage supply are configured to have variable on-resistance. When the charge pump is configured to switch a gain mode from a lower gain to a higher gain, the one or more variable resistance switches are configured to have a decreasing resistance profile over time. In this manner, surge current drawn from the voltage supply at the outset of the gain switch may be limited, while the on-resistance during steady-state charging and discharging may be kept low. Similar techniques are provided to decrease the surge current from a bypass switch coupling the supply voltage to a positive output voltage of the charge pump.

6. 发明申请

WO2012103477A1 HIGH VOLTAGE TOLERANT RECEIVER 审中-公开
标题翻译：高耐压接收器
公开(公告)号：WO2012103477A1
公开(公告)日：2012-08-02
申请号：PCT/US2012/022968
申请日：2012-01-27
申请人： QUALCOMM Incorporated , SRIVASTAVA, Ankit , HUANG, Xuhao , QUAN, Xiaohong
发明人： SRIVASTAVA, Ankit , HUANG, Xuhao , QUAN, Xiaohong
IPC分类号： H03K3/3565 , H03K19/0185
CPC分类号： H03K3/3565 , H03K19/018521
摘要： A high voltage tolerant single ended receiver circuit includes a voltage divider that is operative to divide in half single ended input signals that are greater than the threshold voltages of the voltage divider. A pass gate circuit is operative to receive single ended signals that are below the threshold voltages of the voltage divider. Output from the voltage divider is coupled to a first input of a modified Schmitt trigger circuit to control a high threshold level of the Schmitt trigger circuit. Output from the pass gate circuit is coupled to a second input of the modified Schmitt trigger circuit to control a low threshold level of the Schmitt trigger circuit.
摘要翻译：高耐压单端接收器电路包括分压器，其可操作地将大于分压器的阈值电压的半个单端输入信号分频。通路门电路用于接收低于分压器的阈值电压的单端信号。来自分压器的输出耦合到修改的施密特触发电路的第一输入端，以控制施密特触发电路的高阈值电平。来自通路电路的输出耦合到修改的施密特触发电路的第二输入，以控制施密特触发电路的低阈值电平。

7. 发明申请

WO2012009586A3 SQUELCH DETECTION CIRCUIT AND METHOD 审中-公开
标题翻译：检测电路和方法
公开(公告)号：WO2012009586A3
公开(公告)日：2012-05-18
申请号：PCT/US2011044091
申请日：2011-07-15
申请人： QUALCOMM INC , SRIVASTAVA ANKIT , QUAN XIAOHONG
发明人： SRIVASTAVA ANKIT , QUAN XIAOHONG
IPC分类号： H03G3/34 , H03K5/24
CPC分类号： H04B1/1027 , H03G3/341 , H03K5/2481
摘要： A squelch detection circuit and method involves a first comparator (540) coupled to a complimentary input signal pair (inp, inn) and having a first polarity output. A second comparator (550) coupled to the complimentary input signal pair has a second polarity output. An offset associated with complimentary input signal pair establishes a positive squelch threshold and a negative squelch threshold. A calibration unit (560) coupled to the first comparator and the second comparator generates a digital output including threshold settings and calibration settings to the first comparator and to the second comparator. The digital output can be associated with establishing the offset and with calibrating the positive squelch threshold and the negative squelch threshold.
摘要翻译：静噪检测电路和方法涉及耦合到互补输入信号对（inp，inn）并且具有第一极性输出的第一比较器（540）。耦合到互补输入信号对的第二比较器（550）具有第二极性输出。与补偿输入信号对相关的偏移量建立正静噪阈值和负静噪阈值。耦合到第一比较器和第二比较器的校准单元（560）产生包括阈值设置和校准设置的数字输出到第一比较器和第二比较器。数字输出可以与建立偏移量相关联，并校准正静噪阈值和负静噪阈值。

8. 发明申请

WO2012009586A2 SQUELCH DETECTION CIRCUIT AND METHOD 审中-公开
标题翻译：检测电路和方法
公开(公告)号：WO2012009586A2
公开(公告)日：2012-01-19
申请号：PCT/US2011/044091
申请日：2011-07-15
申请人： QUALCOMM INCORPORATED , SRIVASTAVA, Ankit , QUAN, Xiaohong
发明人： SRIVASTAVA, Ankit , QUAN, Xiaohong
IPC分类号： H03G3/34 , H03K5/24
CPC分类号： H04B1/1027 , H03G3/341 , H03K5/2481
摘要： A squelch detection circuit and method involves a first comparator coupled to a complimentary input signal pair and having a first polarity output. A second comparator coupled to the complimentary input signal pair has a second polarity output. An offset associated with complimentary input signal pair establishes a positive squelch threshold and a negative squelch threshold. A calibration unit coupled to the first comparator and the second comparator generates a digital output including threshold settings and calibration settings to the first comparator and to the second comparator. The digital output can be associated with establishing the offset and with calibrating the positive squelch threshold and the negative squelch threshold.
摘要翻译：静噪检测电路和方法包括耦合到互补输入信号对并具有第一极性输出的第一比较器。耦合到互补输入信号对的第二比较器具有第二极性输出。与补偿输入信号对相关的偏移量建立正静噪阈值和负静噪阈值。耦合到第一比较器和第二比较器的校准单元产生包括阈值设置和校准设置的数字输出到第一比较器和第二比较器。数字输出可以与建立偏移量相关联，并校准正静噪阈值和负静噪阈值。

9. 发明申请

WO2011136964A1 LEVEL SHIFTER FOR DIFFERENTIAL SIGNALS WITH BALANCED TRANSITION TIMES 审中-公开
标题翻译：用于具有平衡过渡时间的差异信号的水平移位
公开(公告)号：WO2011136964A1
公开(公告)日：2011-11-03
申请号：PCT/US2011/032898
申请日：2011-04-18
申请人： QUALCOMM INCORPORATED , SRIVASTAVA, Ankit , QUAN, Xiaohong
发明人： SRIVASTAVA, Ankit , QUAN, Xiaohong
IPC分类号： H03K3/356 , H03K19/003 , H03K5/151 , H03K5/00
CPC分类号： H03K3/356113 , H03K5/151 , H03K19/00323 , H03K2005/00136
摘要： A level shifter (400) and method are provided for balancing rise and fall times of a signal. An input circuit (420, 413) receives a differential logic signal (Inp, Inn) with two complimentary logic levels. A level transition balancing circuit (420) balances the rise and fall times of a level shifted version of each complimentary logic level during a transition from a first to a second of the logic levels and a level shift. A logic element (430) stores and provides outputs (outp, ounn) of the level shifted versions of the logic levels. The level transition balancing circuit (420) includes a capacitor (421) in parallel with a field-effect transistor (422) for each input. The capacitor destabilizes inputs to the logic element and balances the transition using the capacitance and a level (435, 436) previously stored in the logic element.
摘要翻译：提供电平移位器（400）和方法来平衡信号的上升和下降时间。输入电路（420,413）接收具有两个互补逻辑电平的差分逻辑信号（Inp，Inn）。电平转换平衡电路（420）在逻辑电平的第一至第二过渡期间平衡每个互补逻辑电平的电平移位版本的上升和下降时间以及电平偏移。逻辑元件（430）存储并提供逻辑电平的电平转换版本的输出（outp，ounn）。电平转换平衡电路（420）包括与用于每个输入的场效应晶体管（422）并联的电容器（421）。电容器使逻辑元件的输入不稳定，并使用电容和先前存储在逻辑元件中的电平（435,436）平衡转换。

10. 发明申请

WO2012125766A2 CHARGE PUMP SURGE CURRENT REDUCTION 审中-公开
标题翻译：充电泵浪涌电流减少
公开(公告)号：WO2012125766A2
公开(公告)日：2012-09-20
申请号：PCT/US2012029128
申请日：2012-03-14
申请人： QUALCOMM INC , QUAN XIAOHONG , SRIVASTAVA ANKIT , MIAO GUOQING
发明人： QUAN XIAOHONG , SRIVASTAVA ANKIT , MIAO GUOQING
CPC分类号： H02M3/07 , H02M1/36 , H02M2001/0045 , H02M2003/071 , H02M2003/072
摘要： Techniques for reducing surge current in charge pumps. In an exemplary embodiment, one or more switches coupling a terminal of a flying capacitor to a voltage supply are configured to have variable on-resistance. When the charge pump is configured to switch a gain mode from a lower gain to a higher gain, the one or more variable resistance switches are configured to have a decreasing resistance profile over time. In this manner, surge current drawn from the voltage supply at the outset of the gain switch may be limited, while the on-resistance during steady-state charging and discharging may be kept low. Similar techniques are provided to decrease the surge current from a bypass switch coupling the supply voltage to a positive output voltage of the charge pump.
摘要翻译：降低电荷泵浪涌电流的技术。在示例性实施例中，将飞跨电容器的端子耦合到电压源的一个或多个开关被配置为具有可变的导通电阻。当电荷泵被配置为将增益模式从较低增益切换到较高增益时，一个或多个可变电阻开关被配置为具有随时间减小的电阻分布。以这种方式，可以限制在增益开关开始时从电压源引出的浪涌电流，而稳态充放电期间的导通电阻可以保持较低。提供了类似的技术以减少将电源电压耦合到电荷泵的正输出电压的旁路开关的浪涌电流。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式