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1. 发明申请

WO2007029086A2 DERIVATIVES OF 3-AZABICYCLO[3.1.0]HEXANE AS DIPEPTIDYL PEPTIDASE-IV INHIBITORS 审中-公开
标题翻译： 3-亚氨基半胱氨酸[3.1.0] HEXANE作为DIPEPTIDYL PEPTIDASE-IV抑制剂的衍生物
公开(公告)号：WO2007029086A2
公开(公告)日：2007-03-15
申请号：PCT/IB2006/002419
申请日：2006-09-01
申请人： RANBAXY LABORATORIES LIMITED , SATTIGERI, Jitendra, A. , ANDAPPAN, Murugaiah, M S , KISHORE, Kaushal , SETHI, Sachin , KANDALKAR, Sachin, Ramesh , PAL, Chanchal, Kumar , MAHAJAN, Dipak, C. , AHMED, Shahadat , PARKALE, Santhosh, Sadashiv , SRINIVASAN, T , SHARMA, Lalima , BANSAL, Vinay, S. , CHUGH, Anita , DAVIS, Joseph, Alexanand
发明人： SATTIGERI, Jitendra, A. , ANDAPPAN, Murugaiah, M S , KISHORE, Kaushal , SETHI, Sachin , KANDALKAR, Sachin, Ramesh , PAL, Chanchal, Kumar , MAHAJAN, Dipak, C. , AHMED, Shahadat , PARKALE, Santhosh, Sadashiv , SRINIVASAN, T , SHARMA, Lalima , BANSAL, Vinay, S. , CHUGH, Anita , DAVIS, Joseph, Alexanand
CPC分类号： C07D403/12 , C07D209/52 , C07D401/14 , C07D413/14 , C07D417/12 , C07D417/14
摘要： The present invention relates to novel 3-azabicyclo[3.1.0]hexane derivatives as dipeptidyl peptidase-IV inhibitors and the processes for the synthesis of the said compounds. This invention also relates to pharmacological compositions containing the compounds of the present invention, and methods of treating diabetes, especially type 2 diabetes, as well as prediabetes, diabetic dyslipidemia, metabolic acidosis, ketosis, satiety disorders, and obesity. These inhibitors can also be used to treat conditions manifested by a variety of metabolic, neurological, anti-inflammatory, and autoimmune disorders like inflammatory disease, multiple sclerosis, rheumatoid arthritis; viral, cancer and gastrointestinal disorders. The compounds of this invention can also be used for treatment of infertility arising due to polycystic ovary syndrome.
摘要翻译：本发明涉及作为二肽基肽酶-IV抑制剂的新型3-氮杂双环[3.1.0]己烷衍生物及其合成方法。本发明还涉及含有本发明化合物的药物组合物，以及治疗糖尿病，特别是2型糖尿病以及糖尿病前期，糖尿病性血脂异常，代谢性酸中毒，酮症，饱腹感和肥胖症的方法。这些抑制剂也可用于治疗由各种代谢，神经，抗炎和自身免疫性疾病如炎症性疾病，多发性硬化症，类风湿性关节炎，病毒，癌症和胃肠道疾病。本发明的化合物也可用于治疗由于多囊卵巢综合征引起的不育症。

2. 发明申请

WO2007029086A3 DERIVATIVES OF 3-AZABICYCLO[3.1.0]HEXANE AS DIPEPTIDYL PEPTIDASE-IV INHIBITORS 审中-公开
标题翻译： 3-亚氨基半胱氨酸[3.1.0] HEXANE作为DIPEPTIDYL PEPTIDASE-IV抑制剂的衍生物
公开(公告)号：WO2007029086A3
公开(公告)日：2007-05-18
申请号：PCT/IB2006002419
申请日：2006-09-01
申请人： RANBAXY LAB LTD , SATTIGERI JITENDRA A , ANDAPPAN MURUGAIAH M S , KISHORE KAUSHAL , SETHI SACHIN , KANDALKAR SACHIN RAMESH , PAL CHANCHAL KUMAR , MAHAJAN DIPAK C , AHMED SHAHADAT , PARKALE SANTHOSH SADASHIV , SRINIVASAN T , SHARMA LALIMA , BANSAL VINAY S , CHUGH ANITA , DAVIS JOSEPH ALEXANAND
发明人： SATTIGERI JITENDRA A , ANDAPPAN MURUGAIAH M S , KISHORE KAUSHAL , SETHI SACHIN , KANDALKAR SACHIN RAMESH , PAL CHANCHAL KUMAR , MAHAJAN DIPAK C , AHMED SHAHADAT , PARKALE SANTHOSH SADASHIV , SRINIVASAN T , SHARMA LALIMA , BANSAL VINAY S , CHUGH ANITA , DAVIS JOSEPH ALEXANAND
IPC分类号： C07D209/52 , A61K31/439 , A61P3/00 , A61P5/00 , C07D403/12
CPC分类号： C07D403/12 , C07D209/52 , C07D401/14 , C07D413/14 , C07D417/12 , C07D417/14
摘要： The present invention relates to 3-azabicyclo[3.1.0] hexane derivatives of formula (I) as \ dipeptidyl peptidase-IV inhibitors and the processes for the synthesis of the said compounds. This invention also relates to pharmacological compositions containing the compounds of the present invention, and methods of treating diabetes, especially type 2 diabetes, as well as prediabetes, diabetic dyslipidemia, metabolic acidosis, ketosis, satiety disorders, and obesity. These inhibitors can also be used to treat conditions manifested by a variety of metabolic, neurological, anti-inflammatory, and autoimmune disorders like inflammatory disease, multiple sclerosis, rheumatoid arthritis; viral, cancer and gastrointestinal disorders. The compounds of this invention can also be used for treatment . of infertility arising due to polycystic ovary syndrome.
摘要翻译：本发明涉及作为\二肽基肽酶-IV抑制剂的式（I）的3-氮杂双环[3.1.0]己烷衍生物和合成所述化合物的方法。本发明还涉及含有本发明化合物的药物组合物，以及治疗糖尿病，特别是2型糖尿病以及糖尿病前期，糖尿病性血脂异常，代谢性酸中毒，酮症，饱腹感和肥胖症的方法。这些抑制剂也可用于治疗由各种代谢，神经，抗炎和自身免疫性疾病如炎症性疾病，多发性硬化症，类风湿性关节炎，病毒，癌症和胃肠道疾病。本发明的化合物也可用于治疗。由多囊卵巢综合症引起的不育症。

3. 发明授权

US07316003B1 System and method for developing a dynamic web page 有权
标题翻译：用于开发动态网页的系统和方法
公开(公告)号：US07316003B1
公开(公告)日：2008-01-01
申请号：US10322898
申请日：2002-12-18
申请人： Sanjay Dulepet , Stephen Tom , Srinivasan T. Raman , Predrag Petkovic
发明人： Sanjay Dulepet , Stephen Tom , Srinivasan T. Raman , Predrag Petkovic
IPC分类号： G06F9/44
CPC分类号： G06F17/218 , G06F17/2247 , G06F17/272
摘要： A system and method for developing a dynamic web page. An editor facilitates creation and modification of a web page created from static and dynamic web page code. The editor provides a source code view for accessing the dynamic code, static code and static content corresponding to the static code. The editor also provides a visual editor for accessing dynamic content generated from corresponding dynamic code. Modifications to code or content in one view are reflected in the other. A controller generates a merged model of the code and content of the web page. The merged model may be in the form of a hierarchical ordering of nodes, wherein each node corresponds to a code element or a content element. A pre-processor marks dynamic code before the code is deployed, and a post-processor un-marks the dynamic code.
摘要翻译：一种用于开发动态网页的系统和方法。编辑器便于创建和修改从静态和动态网页代码创建的网页。编辑器提供源代码视图，用于访问动态代码，静态代码和与静态代码相对应的静态内容。该编辑器还提供了一个视觉编辑器，用于访问从相应动态代码生成的动态内容。另一个则反映在一个视图中对代码或内容的修改。控制器生成网页的代码和内容的合并模型。合并的模型可以是节点的分级排序的形式，其中每个节点对应于代码元素或内容元素。前处理器在部署代码之前标记动态代码，并且后处理器取消标记动态代码。

4. 发明授权

US06378082B1 Generating strobe signals at different voltage level modes for receiving data at graphics interface port 失效
标题翻译：以不同的电压电平模式生成选通信号，以在图形接口端口接收数据
公开(公告)号：US06378082B1
公开(公告)日：2002-04-23
申请号：US09345711
申请日：1999-06-30
申请人： Srinivasan T. Rajappa , Robert J. Johnston
发明人： Srinivasan T. Rajappa , Robert J. Johnston
IPC分类号： G06F106
CPC分类号： G06F13/4072
摘要： The present invention is a method and apparatus to generate first and second strobe signals to receive data on an interface port of a processor operating in first and second modes at first and second voltage levels, respectively. The second voltage level is higher than the first voltage level. A selector provides first and second selected signals from a plurality of signals which corresponds to the first and second modes. The selector operates at the second voltage level. A signal generator is coupled to the selector to generate the first and second strobe signals from the first and second selected signals.
摘要翻译：本发明是一种生成第一和第二选通信号以在分别以第一和第二电压电平工作的第一和第二模式的处理器的接口端口上接收数据的方法和装置。第二电压电平高于第一电压电平。选择器从对应于第一和第二模式的多个信号提供第一和第二选定信号。选择器工作在第二电压电平。信号发生器耦合到选择器以从第一和第二选择信号产生第一和第二选通信号。

5. 发明授权

US06915407B2 Method and apparatus for a low latency source-synchronous address receiver for a host system bus in a memory controller 有权
标题翻译：用于存储器控制器中的主机系统总线的低延迟源同步地址接收器的方法和装置
公开(公告)号：US06915407B2
公开(公告)日：2005-07-05
申请号：US10813145
申请日：2004-03-30
申请人： Srinivasan T. Rajappa , Romesh B. Trivedi , Rajagopal Subramanian , Zohar Bogin , Serafin Garcia
发明人： Srinivasan T. Rajappa , Romesh B. Trivedi , Rajagopal Subramanian , Zohar Bogin , Serafin Garcia
IPC分类号： G06F13/40 , G06F12/00
CPC分类号： G06F13/4054
摘要： A method and apparatus for a source synchronous address receiver for a system bus. In one embodiment, a flow-through between a system bus address input to a memory bus is controlled by two inputs: one is a source synchronous address strobe directing the receiver to latch the address and store data, while the other is a protocol signal, signaling the beginning of the address transfer. A flow-through circuit generates an enable signal in response to a digital address strobe signal and a digital address select signal to generate, prior to receipt of the address packet, an enable signal for a flow-through gate having the address packet and the enable signal as inputs. The flow-through gate provides the first component of the digital address packet (transaction address) to a chipset once the digital address packet appears on the address pin. Other embodiments are described and claimed.
摘要翻译：一种用于系统总线的源同步地址接收器的方法和装置。在一个实施例中，输入到存储器总线的系统总线地址之间的流通由两个输入来控制：一个是源同步地址选通，指示接收器锁存地址并存储数据，而另一个是协议信号，表示地址转移的开始。流通电路响应于数字地址选通信号和数字地址选择信号产生使能信号，以在接收到地址分组之前生成具有地址分组和使能的流通门的使能信号信号作为输入。数字地址数据包出现在地址引脚上时，流通门将数字地址数据包（交易地址）的第一个分量提供给芯片组。描述和要求保护其他实施例。

6. 发明授权

US06748513B1 Method and apparatus for a low latency source-synchronous address receiver for a host system bus in a memory controller 有权
标题翻译：用于存储器控制器中的主机系统总线的低延迟源同步地址接收器的方法和装置
公开(公告)号：US06748513B1
公开(公告)日：2004-06-08
申请号：US09665922
申请日：2000-09-20
申请人： Srinivasan T. Rajappa , Romesh B. Trivedi , Rajagopal Subramanian , Zohar Bogin , Serafin Garcia
发明人： Srinivasan T. Rajappa , Romesh B. Trivedi , Rajagopal Subramanian , Zohar Bogin , Serafin Garcia
IPC分类号： G06F1200
CPC分类号： G06F13/4054
摘要： A method and apparatus for a source synchronous address receiver for a system bus is described. A flow-through between a system bus address input to a memory bus is controlled by two inputs: one is a source synchronous address strobe directing the receiver to latch the address and store data, while the other is a protocol signal, signaling the beginning of the address transfer. A flow-through circuit generates an enable signal in response to a digital address strobe signal and a digital address select signal to generate, prior to receipt of the address packet, an enable signal for a flow-through gate having the address packet and the enable signal as inputs. The flow-through gate provides the first component of the digital address packet (transaction address) to a chipset once the digital address packet appears on the address pin.
摘要翻译：描述了用于系统总线的源同步地址接收器的方法和装置。输入到存储器总线的系统总线地址之间的流通由两个输入控制：一个是源同步地址选通，指示接收器锁存地址并存储数据，而另一个是协议信号，地址转移。流通电路响应于数字地址选通信号和数字地址选择信号产生使能信号，以在接收到地址分组之前生成具有地址分组和使能的流通门的使能信号信号作为输入。数字地址数据包出现在地址引脚上时，流通门将数字地址数据包（交易地址）的第一个分量提供给芯片组。

7. 发明授权

US06952790B2 System for varying timing between source and data signals in a source synchronous interface 失效
标题翻译：用于在源同步接口中改变源和数据信号之间时序的系统
公开(公告)号：US06952790B2
公开(公告)日：2005-10-04
申请号：US09820898
申请日：2001-03-30
申请人： Girish P. Ramanathan , Srinivasan T. Rajappa
发明人： Girish P. Ramanathan , Srinivasan T. Rajappa
IPC分类号： G01R31/319 , G01R31/3193 , G06F1/04
CPC分类号： G01R31/31922 , G01R31/31937
摘要： A system for measuring timing margins in an interface between a core and an input/output device on a chipset. In order to measure the amount of available variation in data and strobe signals, delay lines are introduced so that the data and strobe signals may be varied in relation to each other. By incrementally changing the delay and hence the time difference between the two signals, it is possible to determine the allowable variation when the device fails to operate. By providing delays on both sides, it is possible to determine the timing margin on both the setup and hold of the signals.
摘要翻译：一种用于测量芯片和芯片组上的输入/输出设备之间的接口中的定时裕度的系统。为了测量数据和选通信号中的可用变化量，引入延迟线，使得数据和选通信号可以相对于彼此变化。通过逐渐改变延迟并因此改变两个信号之间的时间差，可以在设备不能操作时确定允许的变化。通过在两侧提供延迟，可以确定信号的建立和保持的时间裕度。

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