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1. 发明申请

US20150120988A1 Method of Accessing Data in Multi-Layer Cell Memory and Multi-Layer Cell Storage Device Using the Same 审中-公开
标题翻译：在多层单元存储器和多层单元存储设备中访问数据的方法
公开(公告)号：US20150120988A1
公开(公告)日：2015-04-30
申请号：US14064205
申请日：2013-10-28
申请人： Skymedi Corporation
发明人： Chiun-Luen Hung , Yi-Chun Liu
IPC分类号： G06F12/02
CPC分类号： G06F12/0246 , G06F2212/1032 , G06F2212/7202
摘要： A method of accessing data in a multi-layer cell (MLC) memory includes using single-layer cell (SLC) configuration to transfer a portion of a plurality of memory units in the MLC memory to an SLC area to form a plurality of MLC memory units and a plurality of SLC memory units; storing data in the plurality of SLC memory units when the data is assigned to be stored in an MLC memory unit; mapping the MLC memory unit to the SLC memory units; reading the data by obtaining the data in the SLC memory units corresponding to the MLC memory unit; and reallocating the SLC memory units to use MLC configuration when an update of data is involved in the MLC memory unit or a new data is assigned to be stored in at least one of the SLC memory units.
摘要翻译：一种在多层小区（MLC）存储器中访问数据的方法包括使用单层小区（SLC）配置将MLC存储器中的多个存储器单元的一部分传送到SLC区域以形成多个MLC存储器单元和多个SLC存储单元; 当数据被分配存储在MLC存储器单元中时，将数据存储在多个SLC存储器单元中; 将MLC存储器单元映射到SLC存储器单元; 通过获得与MLC存储器单元对应的SLC存储器单元中的数据来读取数据; 以及当MLC存储器单元中涉及更新数据或者将新数据分配存储在至少一个SLC存储器单元中时，将SLC存储器单元重新分配以使用MLC配置。

2. 发明申请

US20140344502A1 Method of Accessing On-Chip Read Only Memory and Computer System Thereof 有权
标题翻译：访问片上只读存储器及其计算机系统的方法
公开(公告)号：US20140344502A1
公开(公告)日：2014-11-20
申请号：US13897439
申请日：2013-05-19
申请人： Skymedi Corporation
发明人： Chia-Jung Hsu , Chih-Cheng Tu , Yun-Chin Lin
IPC分类号： G06F12/06
CPC分类号： G06F13/16 , G06F13/161 , G06F13/1668 , G06F13/1689
摘要： A method of accessing an on-chip read only memory (ROM) includes dividing a frequency of a system clock by a specific divisor, in order to generate a ROM clock; combining a specific number of adjacent addresses into a combined address, wherein the specific number is determined according to the specific divisor; inserting a first stall signal into a real output data, wherein a length of the first stall signal is determined in order to meet a timing requirement for accessing the on-chip ROM; generating an output data of the on-chip ROM according to the combined address, wherein a width of the output data is extended by a specific multiple which is determined according to the specific number; and generating a first delay corresponding to the length of the first stall signal in the address.
摘要翻译：访问片上只读存储器（ROM）的方法包括将系统时钟的频率除以特定因数，以便产生ROM时钟; 将特定数量的相邻地址组合成组合地址，其中所述特定数量根据所述特定因数确定; 将第一失速信号插入到实际输出数据中，其中确定第一失速信号的长度以便满足访问片上ROM的定时要求; 根据组合地址生成片上ROM的输出数据，其中输出数据的宽度被扩展根据特定数量确定的特定倍数; 以及产生与地址中的第一失速信号的长度相对应的第一延迟。

3. 发明申请

US20140229795A1 CONFIGURABLE CODING SYSTEM AND METHOD OF MULTIPLE ECCS 审中-公开
标题翻译：可配置编码系统及多种ECCS方法
公开(公告)号：US20140229795A1
公开(公告)日：2014-08-14
申请号：US14254530
申请日：2014-04-16
申请人： Skymedi Corporation
发明人： Yu-Shuen TANG , Chuang Cheng
IPC分类号： H03M13/11 , G06F11/10
CPC分类号： H03M13/1105 , G06F11/10 , G06F11/1016 , H03M13/1102 , H03M13/152 , H03M13/353 , H03M13/3707 , H03M13/6511 , H03M13/6513 , H03M13/6516
摘要： A configurable coding system and method of multiple error correcting codes (ECCs) for a memory device or devices are disclosed. The system includes a first ECC codec that selectively performs different error corrections with different parameters; means for providing a selected parameter to the ECC codec for initializing the ECC codec; and a second ECC codec that corrects the selected error-prone parameter in order to provide an error-free parameter to the first ECC codec.
摘要翻译：公开了一种用于存储器件或设备的多个纠错码（ECC）的可配置编码系统和方法。该系统包括第一ECC编解码器，其选择性地执行具有不同参数的不同误差校正; 用于将ECC选择参数提供给ECC编解码器以便初始化ECC编解码器的装置; 以及第二ECC编解码器，其校正所选择的容易出错参数，以便向第一ECC编解码器提供无错参数。

4. 发明申请

US20140201253A1 Delay Device, Method, and Random Number Generator Using the Same 有权
标题翻译：延迟设备，方法和使用它的随机数生成器
公开(公告)号：US20140201253A1
公开(公告)日：2014-07-17
申请号：US13742357
申请日：2013-01-16
申请人： SKYMEDI CORPORATION
发明人： Feng-Shen Chu
IPC分类号： G06F7/58
CPC分类号： G06F7/582 , G06F7/588 , H03K3/84
摘要： A delay device for generating a signal for a random component in a random number generator is disclosed. The delay device includes a delay module, for generating a plurality of delayed signals, wherein each delayed signal has a delay time and the delay time is different from each other; a first multiplexer, coupled to the delay module, for outputting a delayed signal among the plurality of delayed signals as a delayed trigger signal to control the random component to generate a random bit; and a delay selector, coupled to the first multiplexer, for generating a selecting signal to control the first multiplexer to select to output the delayed signal as the delayed trigger signal.
摘要翻译：公开了一种用于产生随机数发生器中的随机分量的信号的延迟装置。所述延迟装置包括用于产生多个延迟信号的延迟模块，其中每个延迟信号具有延迟时间并且所述延迟时间彼此不同; 耦合到所述延迟模块的第一多路复用器，用于输出所述多个延迟信号中的延迟信号作为延迟触发信号，以控制所述随机分量以产生随机位; 以及延迟选择器，耦合到第一多路复用器，用于产生选择信号以控制第一多路复用器选择输出延迟的信号作为延迟的触发信号。

5. 发明申请

US20140237143A1 Debugging Fixture 审中-公开
标题翻译：调试夹具
公开(公告)号：US20140237143A1
公开(公告)日：2014-08-21
申请号：US13772366
申请日：2013-02-21
申请人： SKYMEDI CORPORATION
发明人： Bo-Wen Hsiao , Ding-Yun Chen
IPC分类号： G06F9/44
CPC分类号： G06F13/4068 , G06F2213/0042
摘要： A fixture, for connecting a host device and a universal serial bus (USB) device, the fixture comprises a plurality of connectors; a plurality of first signal pins, located at first ends of the plurality of connectors for connecting to the host device; and a plurality of second signal pins, located at second ends of the plurality of connectors for connecting to the USB device; wherein a first part of the plurality of connectors are used for transmitting signals between the host device and the USB device in a USB mode; wherein a second part of the plurality of connectors are retained in a specified state for providing a control signal to control the USB device to enter an operating mode.
摘要翻译：一种用于连接主机设备和通用串行总线（USB）设备的固定装置，所述固定装置包括多个连接器; 多个第一信号引脚，位于多个连接器的第一端，用于连接到主机设备; 以及多个第二信号引脚，位于所述多个连接器的第二端，用于连接到所述USB设备; 其中所述多个连接器的第一部分用于以USB模式在所述主机设备和所述USB设备之间传输信号; 其中所述多个连接器的第二部分保持在指定状态，以提供控制信号以控制所述USB设备进入操作模式。

6. 发明申请

US20140181621A1 METHOD OF ARRANGING DATA IN A NON-VOLATILE MEMORY AND A MEMORY CONTROL SYSTEM THEREOF 审中-公开
标题翻译：在非易失性存储器中安装数据的方法及其存储器控制系统
公开(公告)号：US20140181621A1
公开(公告)日：2014-06-26
申请号：US13727487
申请日：2012-12-26
申请人： SKYMEDI CORPORATION
发明人： Ting-Wei Lin , You-Chang Hsiao
IPC分类号： G06F11/10
CPC分类号： G11C29/808 , G11C29/82
摘要： A method of arranging data in a non-volatile memory and an associated memory control system are disclosed. A data area is divided into a plurality of valid data divisions, each having a link header followed by associated data and error correction code (ECC). At least one linking parameter is set in each said link header, and at least one obsolete data division including a bad column or columns is set, each said obsolete data division being flexible in size. Valid data divisions are linked and the obsolete data divisions are skipped, when accessing the non-volatile memory, according to the at least one linking parameter.
摘要翻译：公开了一种在非易失性存储器和相关的存储器控制系统中排列数据的方法。数据区被划分为多个有效的数据部分，每个数据部分具有链接头部，随后是相关联的数据和纠错码（ECC）。在每个所述链接头中设置至少一个链接参数，并且设置包括坏列或列的至少一个过时的数据部分，每个所述过时的数据部分的大小是灵活的。根据至少一个链接参数，当访问非易失性存储器时，链接有效数据划分并且过时的数据划分被跳过。

7. 发明申请

US20140137128A1 Method of Scheduling Tasks for Memories and Memory System Thereof 有权
标题翻译：记忆和记忆系统任务调度方法
公开(公告)号：US20140137128A1
公开(公告)日：2014-05-15
申请号：US13674106
申请日：2012-11-12
申请人： SKYMEDI CORPORATION
发明人： Yu-Tang Chang , Yi-Chun Liu
IPC分类号： G06F9/46
CPC分类号： G06F9/4881 , G06F3/061 , G06F3/0625 , G06F3/0659 , G06F3/0679 , G06F13/1642 , G06F2209/486 , Y02D10/154 , Y02D10/24
摘要： A method of scheduling a plurality of tasks for a plurality of memories in a memory system is disclosed. The method includes classifying each task among the plurality of tasks to a task type among a plurality of task types, disposing a plurality of task queues according to the plurality of task types wherein each task queue stores tasks to be executed within the plurality of tasks, assigning a priority for each task type among the plurality of task types, disposing at least one execution queue; and converting a first task stored in a first task queue among the plurality of task queues into at least one command to be stored in a first execution queue among the at least one execution queue, wherein the at least one command is executed according to the priority of a first task type corresponding to the first task queue.
摘要翻译：公开了一种在存储器系统中调度多个存储器的多个任务的方法。该方法包括将多个任务中的每个任务分类为多个任务类型中的任务类型，根据多个任务类型布置多个任务队列，其中每个任务队列存储多个任务内要执行的任务，为所述多个任务类型中的每个任务类型分配优先级，设置至少一个执行队列; 以及将所述多个任务队列中存储在第一任务队列中的第一任务转换为至少一个要存储在所述至少一个执行队列中的第一执行队列中的命令，其中根据所述优先级执行所述至少一个命令对应于第一任务队列的第一任务类型。

8. 发明申请

US20130179749A1 METHOD AND SYSTEM OF DYNAMIC DATA STORAGE FOR ERROR CORRECTION IN A MEMORY DEVICE 有权
标题翻译：用于存储器件中的错误校正的动态数据存储的方法和系统
公开(公告)号：US20130179749A1
公开(公告)日：2013-07-11
申请号：US13783069
申请日：2013-03-01
申请人： SKYMEDI CORPORATION
发明人： CHIH-CHENG TU , YAN-WUN HUANG , HAN-LUNG HUANG , MING-HUNG CHOU , CHIEN-FU HUANG , CHIH-HWA CHANG
IPC分类号： H03M13/05
CPC分类号： H03M13/05 , G06F11/1068 , G11C2029/0411 , H03M13/13
摘要： A method of dynamic data storage for error correction in a memory device is disclosed. Data for storage is received, the received data is encoded and error correction code (ECC) is generated. The encoded data is stored in the memory device that includes a plurality of pages each having a plurality of data partitions. More corrected errors a marked page has, a smaller portion with a space of at least one datum of each of the corresponding data partitions associated with the marked page is allocated to store the encoded data, while a size of the ECC is fixed, thereby increasing capability of correcting errors in the marked page.
摘要翻译：公开了一种用于存储器件中的纠错的动态数据存储的方法。接收用于存储的数据，对接收的数据进行编码，并生成纠错码（ECC）。编码数据存储在包括多个页面的存储设备中，每个页面具有多个数据分区。分配标记页面的更正校正的错误，分配具有与标记页面相关联的每个相应数据分区的至少一个基准的空间的较小部分以存储编码数据，同时ECC的大小固定，从而增加纠正标记页面错误的能力。

9. 发明申请

US20150349805A1 Method of Handling Error Correcting Code in Non-volatile Memory and Non-volatile Storage Device Using the Same 审中-公开
标题翻译：在非易失性存储器和非易失性存储设备中处理纠错码的方法使用该方法
公开(公告)号：US20150349805A1
公开(公告)日：2015-12-03
申请号：US14289627
申请日：2014-05-28
申请人： Skymedi Corporation
发明人： Tzung-Shiang Tsai , Chia-Chen Chang
IPC分类号： H03M13/29 , H03M13/00
CPC分类号： H03M13/2906 , G06F11/1012 , H03M13/2942 , H03M13/35 , H03M13/6312
摘要： A method of handling an error correcting code (ECC) in a non-volatile memory includes performing a first ECC operation on data codes to generate first parity codes; compressing the first parity codes to generate compressed parity codes; performing a second ECC operation on the compressed parity codes to generate additional parity codes; and writing the data codes, the compressed parity codes and the additional parity codes into a memory unit of the non-volatile memory.
摘要翻译：在非易失性存储器中处理纠错码（ECC）的方法包括对数据码执行第一ECC操作以产生第一奇偶校验码; 压缩第一奇偶校验码以产生压缩奇偶校验码; 对压缩的奇偶校验码执行第二ECC操作以产生附加奇偶校验码; 以及将数据代码，压缩奇偶校验码和附加奇偶校验码写入到非易失性存储器的存储器单元中。

10. 发明授权

US09141566B2 Method of accessing on-chip read only memory and computer system thereof 有权
标题翻译：访问片上只读存储器及其计算机系统的方法
公开(公告)号：US09141566B2
公开(公告)日：2015-09-22
申请号：US13897439
申请日：2013-05-19
申请人： Skymedi Corporation
发明人： Chia-Jung Hsu , Chih-Cheng Tu , Yun-Chin Lin
IPC分类号： G06F12/06 , G06F13/16
CPC分类号： G06F13/16 , G06F13/161 , G06F13/1668 , G06F13/1689
摘要： A method of accessing an on-chip read only memory (ROM) includes dividing a frequency of a system clock by a specific divisor, in order to generate a ROM clock; combining a specific number of adjacent addresses into a combined address, wherein the specific number is determined according to the specific divisor; inserting a first stall signal into a real output data, wherein a length of the first stall signal is determined in order to meet a timing requirement for accessing the on-chip ROM; generating an output data of the on-chip ROM according to the combined address, wherein a width of the output data is extended by a specific multiple which is determined according to the specific number; and generating a first delay corresponding to the length of the first stall signal in the address.
摘要翻译：访问片上只读存储器（ROM）的方法包括将系统时钟的频率除以特定因数，以便产生ROM时钟; 将特定数量的相邻地址组合成组合地址，其中所述特定数量根据所述特定因数确定; 将第一失速信号插入到实际输出数据中，其中确定第一失速信号的长度以便满足访问片上ROM的定时要求; 根据组合地址生成片上ROM的输出数据，其中输出数据的宽度被扩展根据特定数量确定的特定倍数; 以及产生与地址中的第一失速信号的长度相对应的第一延迟。

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