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1. 发明申请

WO2009046306A1 ACCELERATOR PARTICLE BEAM APPARATUS AND METHOD FOR LOW CONTAMINATE PROCESSING 审中-公开
标题翻译：加速器颗粒光束装置和低污染处理方法
公开(公告)号：WO2009046306A1
公开(公告)日：2009-04-09
申请号：PCT/US2008/078760
申请日：2008-10-03
申请人： SILICON GENESIS CORPORATION , HENLEY, Francois, J. , LAAM, Albert , BRAILOVE, Adam , ADIBI, Babak
发明人： HENLEY, Francois, J. , LAAM, Albert , BRAILOVE, Adam , ADIBI, Babak
IPC分类号： H01J37/08
CPC分类号： H01J37/3171 , H01J2237/022 , H01J2237/04735 , H01J2237/057 , H01J2237/18 , H01J2237/31705 , H01L21/76254
摘要： A system of introducing a particle beam such as a linear accelerator particle beam for low contaminate processing. The system includes an accelerator apparatus configured to generate a first particle beam including at least a first ionic specie in an energy level 1 MeV to 5 MeV or greater. Additionally, the system includes a beam filter coupled to the linear accelerator apparatus to receive the first particle beam. The beam filter is in a first chamber and configured to generate a second particle beam with substantially the first ionic specie only. The first chamber is associated with a first pressure. The system further includes an end-station including a second chamber coupled to the first chamber for extracting the second particle beam. The second particle beam is irradiated onto a planar surface of a bulk workpiece loaded in the second chamber for implanting the first ionic specie.
摘要翻译：引入粒子束的系统，例如用于低污染处理的线性加速器粒子束。该系统包括加速器装置，该加速器装置被配置为产生第一粒子束，该第一粒子束至少包括能量级MeV至5MeV或更大的第一离子物质。另外，该系统包括耦合到线性加速器装置以接收第一粒子束的束过滤器。束过滤器位于第一室中，并且被配置为仅产生基本上为第一离子物质的第二粒子束。第一室与第一压力相关。该系统还包括终端站，其包括耦合到第一室的第二室，用于提取第二粒子束。将第二粒子束照射到装载在第二室中的体积工件的平坦表面上，用于植入第一离子物质。

2. 发明申请

WO2007114974A2 METHOD AND STRUCTURE FOR FABRICATING BONDED SUBSTRATE STRUCTURES USING THERMAL PROCESSING TO REMOVE OXYGEN SPECIES 审中-公开
标题翻译：使用热处理去除氧气物种的结合基板结构的方法和结构
公开(公告)号：WO2007114974A2
公开(公告)日：2007-10-11
申请号：PCT/US2007/060801
申请日：2007-01-19
申请人： SILICON GENESIS CORPORATION , HENLEY, Francois, J. , SULLIVAN, James, Andrew , KANG, Sien, Giok , ONG, Philip, James , KIRK, Harry, Robert , JACY, David
发明人： HENLEY, Francois, J. , SULLIVAN, James, Andrew , KANG, Sien, Giok , ONG, Philip, James , KIRK, Harry, Robert , JACY, David
IPC分类号： G06Q10/00 , G06Q40/00
CPC分类号： H01L21/76254
摘要： A method for fabricating bonded substrate structures, e.g., silicon on silicon. In a specific embodiment, the method includes providing a thickness of single crystal silicon material transferred from a first silicon substrate coupled to a second silicon substrate. In a specific embodiment, the second silicon substrate has a second surface region that is joined to a first surface region from the thickness of single crystal silicon material to form of an interface region having a first characteristic including a silicon oxide material between the thickness of single crystal silicon material and the second silicon substrate. The method includes subjecting the interface region to a thermal process to cause a change to the interface region from the first characteristic to a second characteristic. In a specific embodiment, the second characteristic is free from the silicon oxide material and is an epitaxially formed silicon material provided between the thickness of single crystal silicon material and the second silicon substrate. The method includes maintaining the interface region free of multiple voids during the thermal process to form the epitaxially formed silicon material to electrically couple the thickness of single crystal silicon material to the second silicon substrate.
摘要翻译：一种制造键合衬底结构的方法，例如硅上的硅。在具体实施例中，该方法包括提供从耦合到第二硅衬底的第一硅衬底转移的单晶硅材料的厚度。在具体实施例中，第二硅衬底具有第二表面区域，该第二表面区域从单晶硅材料的厚度连接到第一表面区域，以形成具有第一特征的界面区域，该第一特征包括单一厚度的氧化硅材料晶体硅材料和第二硅衬底。该方法包括使界面区域进行热处理以使接口区域从第一特性改变到第二特性。在具体实施方案中，第二特性不含氧化硅材料，并且是设置在单晶硅材料的厚度与第二硅衬底之间的外延形成的硅材料。该方法包括在热处理期间保持界面区域没有多个空隙以形成外延形成的硅材料，以将单晶硅材料的厚度电耦合到第二硅衬底。

3. 发明申请

WO2004034453A1 METHOD FOR TREATING SEMICONDUCTOR MATERIAL 审中-公开
标题翻译：用于处理半导体材料的方法
公开(公告)号：WO2004034453A1
公开(公告)日：2004-04-22
申请号：PCT/US2003/031404
申请日：2003-10-03
申请人： SILICON GENESIS CORPORATION
发明人： MALIK, Igor, J. , KANG, Sien, G. , FUERFANGER, Martin , KIRK, Harry , FLAT, Ariel , CURRENT, Michael, Ira , ONG, Philip, James
IPC分类号： H01L21/3065
CPC分类号： C30B33/00 , H01L21/02381 , H01L21/0243 , H01L21/0245 , H01L21/02532 , H01L21/02573 , H01L21/02658 , H01L21/3065
摘要： The present invention provides a method of forming a strained semiconductor layer. The method comprises growing a strained semiconductor layer, having a first lattice constant, on a wafer. The method further comprises etch annealing the strained semiconductor layer, wherein the strained semiconductor layer is relaxed. The methodcontrols the surface roughness of the semiconductor layers. The method also has the unexpected benefit of reducing dislocations in the semiconductor layers.
摘要翻译：本发明提供一种形成应变半导体层的方法。该方法包括在晶片上生长具有第一晶格常数的应变半导体层。该方法还包括对应变半导体层进行蚀刻退火，其中应变半导体层被松弛。该方法控制半导体层的表面粗糙度。该方法还具有减少半导体层中位错的意想不到的好处。

4. 发明申请

WO2023060004A1 THREE DIMENSIONAL INTEGRATED CIRCUIT WITH LATERAL CONNECTION LAYER 审中-公开
公开(公告)号：WO2023060004A1
公开(公告)日：2023-04-13
申请号：PCT/US2022/077180
申请日：2022-09-28
申请人： SILICON GENESIS CORPORATION
发明人： CURRENT, Michael I. , FONG, Theodore E.
IPC分类号： H01L25/00 , H01L21/48 , H01L21/60 , H01L21/768 , H01L21/78 , H01L23/00 , H01L25/065 , H01L21/26506 , H01L21/486 , H01L21/76802 , H01L2224/08145 , H01L2224/08146 , H01L2224/09181 , H01L2224/19 , H01L2224/20 , H01L2224/73251 , H01L2224/73259 , H01L2224/80006 , H01L2224/80203 , H01L2224/80357 , H01L2224/80895 , H01L2224/80896 , H01L2224/80986 , H01L2224/9222 , H01L2225/06513 , H01L2225/06548 , H01L2225/06572 , H01L2225/06589 , H01L23/473 , H01L24/08 , H01L24/80 , H01L24/95 , H01L25/0652 , H01L25/0657 , H01L25/50
摘要： Forming a 3DIC includes providing a lower device structure comprising a first substrate with a circuit layer, providing an interconnect network layer having an interconnect structure with a first coupled to a second plurality of electrodes by connection structures on a semiconductor substrate, the first plurality of electrodes being exposed on a first surface of the interconnect layer, implanting ions through the interconnect structure to form a cleave plane in the semiconductor substrate, bonding the interconnect structure to the lower device structure so that electrodes of the first plurality of electrodes are coupled to corresponding electrodes on the lower device structure, cleaving the substrate of the bonded interconnect layer at the cleave plane, removing material from the semiconductor substrate until the second plurality of electrodes is exposed, and bonding an upper device layer to the interconnect structure.

5. 发明申请

WO2008058131A2 METHOD AND STRUCTURE FOR THICK LAYER TRANSFER USING A LINEAR ACCELERATOR 审中-公开
标题翻译：使用线性加速器的厚层转移方法和结构
公开(公告)号：WO2008058131A2
公开(公告)日：2008-05-15
申请号：PCT/US2007/083784
申请日：2007-11-06
申请人： SILICON GENESIS CORPORATION , HENLEY, Francois, J. , LAMM, Albert , ADIBI, Babak
发明人： HENLEY, Francois, J. , LAMM, Albert , ADIBI, Babak
IPC分类号： H01L21/20
CPC分类号： H01L21/76254 , H01L21/26506 , H01L21/3221
摘要： A method for fabricating free standing thickness of materials using one or more semiconductor substrates, e.g., single crystal silicon, polysilicon, silicon germanium, germanium, group III/IV materials, and others. In a specific embodiment, the present method includes providing a semiconductor substrate having a surface region and a thickness. The method includes subjecting the surface region of the semiconductor substrate to a first plurality of high energy particles generated using a linear accelerator to form a region of a plurality of gettering sites within a cleave region, the cleave region being provided beneath the surface region to defined a thickness of material to be detached, the semiconductor substrate being maintained at a first temperature. In a specific embodiment, the method includes subjecting the surface region of the semiconductor substrate to a second plurality of high energy particles generated using the linear accelerator, the second plurality of high energy particles being provided to increase a stress level of the cleave region from a first stress level to a second stress level. In a preferred embodiment, the semiconductor substrate is maintained at a second temperature, which is higher than the first temperature. The method frees the thickness of detachable material using a cleaving process, e.g., controlled cleaving process.
摘要翻译：利用一个或多个半导体衬底（例如，单晶硅，多晶硅，硅锗，锗，III / IV族材料等）制造材料的独立厚度的方法。在具体实施例中，本方法包括提供具有表面区域和厚度的半导体衬底。该方法包括使半导体衬底的表面区域经受使用线性加速器产生的第一多个高能粒子以在劈裂区域内形成多个吸杂位置的区域，劈裂区域设置在表面区域的下方以限定待分离材料的厚度，半导体衬底保持在第一温度。在特定实施例中，该方法包括使半导体衬底的表面区域经受使用线性加速器产生的第二多个高能粒子，提供第二多个高能粒子以增加劈裂区域的应力水平从第一应力水平至第二应力水平。在优选实施例中，半导体衬底保持在高于第一温度的第二温度。该方法使用切割工艺（例如受控切割工艺）释放可分离材料的厚度。

6. 发明申请

WO2007118121A3 METHOD AND STRUCTURE FOR FABRICATING SOLAR CELLS USING A LAYER TRANSFER PROCESS 审中-公开
公开(公告)号：WO2007118121A3
公开(公告)日：2007-10-18
申请号：PCT/US2007/065964
申请日：2007-04-04
申请人： SILICON GENESIS CORPORATION , HENLEY, Francois, J.
发明人： HENLEY, Francois, J.
IPC分类号： H01L21/00 , H01L25/00 , H01L31/00 , H02N6/00
摘要： A reusable silicon substrate device for use with layer transfer process. The device has a reusable substrate having a surface region, a cleave region, and a total thickness of material. The total thickness of material is at least N times greater than a first thickness of material to be removed. In a specific embodiment, the first thickness of material to be removed is between the surface region and the cleave region, whereupon N is an integer greater than about ten. The device also has a chuck member adapted to hold a handle substrate member in place. The chuck member is configured to hold the handle substrate in a manner to facilitate bonding the handle substrate to the first thickness of material to be removed. In a preferred embodiment, the device has a mechanical pressure device operably coupled to the chuck member. The mechanical pressure device is adapted to provide a force to cause bonding of the handle substrate to the first thickness of material to be removed.

7. 发明申请

WO2007019544A3 PRE-MADE CLEAVABLE SUBSTRATE AND DEVICES USING FILMS PROVIDED BY A LAYER TRANSFER PROCESS 审中-公开
公开(公告)号：WO2007019544A3
公开(公告)日：2007-02-15
申请号：PCT/US2006/031033
申请日：2006-08-08
申请人： SILICON GENESIS CORPORATION , HENLEY, Francois, J.
发明人： HENLEY, Francois, J.
IPC分类号： B29C63/00 , H01L27/00 , H01L21/46
摘要： A method for fabricating one or more devices, e.g., integrated circuits. The method includes providing a multi-layered substrate, which has a thickness of material (e.g., single crystal silicon) overlying a first debondable surface coupled to and overlying a second debondable surface. The second debondable surface is overlying an interface region of the multi-layered substrate. In a preferred embodiment, the thickness of material having a surface region. The method includes processing the surface region of the multi-layered substrate using one or more processes to form at least one device onto a portion of the surface region. The method includes forming a planarized upper surface region overlying the surface region of the thickness of material. The method includes joining the planarized upper surface region to a face of a handle substrate. In a preferred embodiment, the method includes processing the first debondable surface and the second debondable surface to change a bond strength from a first determined amount to a second determined amount, which is capable of debonding the first debondable surface from the second debondable surface. The method includes debonding the first debondable surface from the second debondable surface to release the thickness of material and the handle substrate.

8. 发明申请

WO2006058076A2 METHOD AND STRUCTURE FOR IMPLANTING BONDED SUBSTRATES FOR ELECTRICAL CONDUCTIVITY 审中-公开
标题翻译：用于电连接的粘结基板的方法和结构
公开(公告)号：WO2006058076A2
公开(公告)日：2006-06-01
申请号：PCT/US2005/042457
申请日：2005-11-22
申请人： SILICON GENESIS CORPORATION , HENLEY, Francois, J.
发明人： HENLEY, Francois, J.
IPC分类号： H01L29/00
CPC分类号： H01L21/26513
摘要： A process for forming multi-layered substrates, e.g ., silicon on silicon. The process includes providing a first substrate, which has a thickness of material to be removed. The thickness of material to be removed includes a first face region. The process includes joining the first face region of the first substrate to a second face region of a second substrate to form an interface region between the first face region of the first substrate and the second face region of the second substrate. The process includes removing the thickness of material from the first substrate while maintaining attachment of the first face region of the first substrate to the second face region of the second substrate. The process implants particles through the interface region to form a region of the particles within the vicinity of the interface region to electrically couple the thickness of material to the second substrate. In a preferred embodiment, the particles are conductive or can also have other characteristics that facilitates electrical contact or coupling between the first face region and the second face region according to a specific embodiment.
摘要翻译：用于形成多层基板的方法，例如硅上的硅。该方法包括提供第一基底，其具有待除去的材料的厚度。要去除的材料的厚度包括第一面区域。该方法包括将第一衬底的第一面区域连接到第二衬底的第二面区域，以在第一衬底的第一面区域和第二衬底的第二面区域之间形成界面区域。该方法包括从第一基板去除材料的厚度，同时保持第一基板的第一面区域与第二基板的第二面区域的连接。该过程通过界面区域投入颗粒以在界面区域附近形成颗粒的区域，以将材料的厚度电耦合到第二基底。在优选实施例中，根据具体实施例，颗粒是导电的或者还可以具有促进第一面区域和第二面部区域之间的电接触或耦合的其它特性。

9. 发明申请

WO2005101465A2 METHOD AND SYSTEM FOR LATTICE SPACE ENGINEERING 审中-公开
标题翻译：空间工程方法与系统
公开(公告)号：WO2005101465A2
公开(公告)日：2005-10-27
申请号：PCT/US2005/012410
申请日：2005-04-12
申请人： SILICON GENESIS CORPORATION , HENLEY, Francois, J. , ONG, Philip, James , MALIK, Igor, J.
发明人： HENLEY, Francois, J. , ONG, Philip, James , MALIK, Igor, J.
IPC分类号： H01L21/00
CPC分类号： H01L21/2007 , H01L21/76251
摘要： A system for manufacturing multilayered substrates. The system has a support member is adapted to process a film of material comprising a first side and a second side from a first state to a second state. The support member is attached to the first side of the film of material. The second state comprises a stressed state. The system has a handle substrate comprising a face, which is adapted to be attached to the second side of the film of material. The support member is capable of being detached from the first side of the film of material thereby leaving the handle substrate comprising the film of material in the second state being attached to the face of the handle substrate.
摘要翻译：一种用于制造多层基片的系统。该系统具有支撑构件，适于处理包括从第一状态到第二状态的第一侧和第二侧的材料膜。支撑构件附接到材料膜的第一侧。第二种状态包括压力状态。该系统具有手柄基板，该基板包括面，该表面适于附接到材料膜的第二侧。支撑构件能够从材料膜的第一侧分离，从而将包括处于第二状态的材料膜的手柄基板附接到手柄基板的表面。

10. 发明申请

WO2005067682A3 AN APPARATUS AND METHOD FOR CONTROLLED CLEAVING 审中-公开
公开(公告)号：WO2005067682A3
公开(公告)日：2005-07-28
申请号：PCT/US2005/000747
申请日：2005-01-10
申请人： SILICON GENESIS CORPORATION , HENLEY, Francois, J. , TEOH, Hongbee , PALER, Anthony , LAMM, Albert , ONG, Philip
发明人： HENLEY, Francois, J. , TEOH, Hongbee , PALER, Anthony , LAMM, Albert , ONG, Philip
IPC分类号： B32B1/00
摘要： An Apparatus and method for controlled cleaving is presented. Embodiments of the present invention include an apparatus for cleaving a substrate comprising a bottom shell coupled to a hinge mechanism, a top shell coupled to the hinge mechanism, a plurality of o-rings or suction cups coupled to the top and bottom shells for providing a suction force sufficient to exert a tensile force to the top and bottom of a substrate, a compliant member for sealing a portion of a grove edge of a substrate and for maintaining a pressure inside a volume formed between the groove edge and the groove edge of the substrate, a gas port for supplying gas to the volume, and a height adjustment mechanism coupled to the top shell and the bottom shell for separating the top shell from the bottom shell. One embodiment of the invention eliminates the use of gas system and is replaced by a blade edge to initiate propagation and applied tensile force of suction cups to apply tensile forces prior to initiation, control cleave process and maintain layer separation during and after cleaving.

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