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1. 发明申请

WO0182496A3 LONG SUBSCRIBER LOOPS USING AUTOMATIC GAIN CONTROL 审中-公开
标题翻译：使用自动增益控制的长订阅者鞋
公开(公告)号：WO0182496A3
公开(公告)日：2002-05-10
申请号：PCT/US0140623
申请日：2001-04-26
申请人： SYMMETRICOM INC , SOMMER JEREMY , SHENOI KISHAN , KRABA KAMILA , SQUADRITO SANDRO , BOGARDUS GARY
发明人： SOMMER JEREMY , SHENOI KISHAN , KRABA KAMILA , SQUADRITO SANDRO , BOGARDUS GARY
IPC分类号： H04B3/06 , H04L25/24 , H04B3/38 , H04L27/26
CPC分类号： H04B3/06 , H04L25/24
摘要： Systems and methods are described for long subscriber loops using automatic gain control. A method includes extending a digital subscriber loop including: producing an output signal from said first variable gain amplifier responsive to an input signal from said digital subscriber loop; monitoring a signal strength of said output signal; generating a gain control signal responsive to said signal strength; and controlling a gain of said variable gain amplifier responsive to said gain control signal. An apparatus includes a digital subscriber loop extender circuit including: a variable gain amplifier having a gain and providing an output signal in response to an input signal from a signal generator over a transmission medium, said output signal having a signal strength as a function of said gain; and a controller coupled to said variable gain amplifier, said controller generating a gain control signal that is fed back to said variable gain amplifier to automatically control said gain.
摘要翻译：对使用自动增益控制的长用户回路描述系统和方法。一种方法包括扩展数字用户环路，包括：响应于来自所述数字用户环路的输入信号，产生来自所述第一可变增益放大器的输出信号; 监视所述输出信号的信号强度; 产生响应于所述信号强度的增益控制信号; 以及响应于所述增益控制信号来控制所述可变增益放大器的增益。一种装置包括：数字用户环路延长器电路，包括：可变增益放大器，具有增益并响应于来自信号发生器的传输介质的输入信号提供输出信号，所述输出信号具有作为所述信号发生器的函数的信号强度获得; 以及耦合到所述可变增益放大器的控制器，所述控制器产生反馈到所述可变增益放大器以自动控制所述增益的增益控制信号。

2. 发明申请

WO2002069536A1 MEASUREMENT OF TIME-DELAY, TIME-DELAY-VARIATION, AND CELL TRANSFER RATE IN ATM NETWORKS 审中-公开
标题翻译： ATM网络中时间延迟，时间延迟和小区传输速率的测量
公开(公告)号：WO2002069536A1
公开(公告)日：2002-09-06
申请号：PCT/US2002/006056
申请日：2002-02-28
申请人： SYMMETRICOM, INC. , SHENOI, Kishan , JACOBSEN, Gary , KRABA, Kamila , LAI, Chien-Chou , SOMMER, Jeremy , YANG, Jining
发明人： SHENOI, Kishan , JACOBSEN, Gary , KRABA, Kamila , LAI, Chien-Chou , SOMMER, Jeremy , YANG, Jining
IPC分类号： H04J3/06
CPC分类号： H04L12/5601
摘要： Systems and methods are described for the measurement of time delay, time delay variation and cell transfer rate in asynchronous transfer mode networks. A method includes generating a time-stamp information cell at a first location; transmitting the time-stamp information cell to a second location via a network link; and receiving the time-stamp information cell at the second location. An apparatus includes an asynchronous transfer mode network including a time delay information cell generator.
摘要翻译：描述了用于测量异步传输模式网络中的时间延迟，时间延迟变化和小区传输速率的系统和方法。一种方法包括在第一位置产生时间戳信息单元; 经由网络链路将时间戳信息单元发送到第二位置; 以及在所述第二位置处接收所述时间戳信息单元。一种装置包括包括时间延迟信息单元发生器的异步传输模式网络。

3. 发明申请

WO2002069574A1 MULTI-LINK SEGMENTATION AND REASSEMBLY FOR BONDING MULTIPLE PVC'S IN AN INVERSE MULTIPLEXING ARRANGEMENT 审中-公开
标题翻译：多链路分段和重新组合将多个PVC结合在一个反向复用安排中
公开(公告)号：WO2002069574A1
公开(公告)日：2002-09-06
申请号：PCT/US2002/005878
申请日：2002-02-28
申请人： SYMMETRICOM, INC. , SHENOI, Kishan , JACOBSON, Gary , KRABA, Kamila , LAI, Chien-Chou , SOMMER, Jeremy , YANG, Jining
发明人： SHENOI, Kishan , JACOBSON, Gary , KRABA, Kamila , LAI, Chien-Chou , SOMMER, Jeremy , YANG, Jining
IPC分类号： H04L12/28
CPC分类号： H04L12/5601
摘要： Systems and methods are described for multi-link segmentation and reassembly for bonging multiple virtual circuits (802) in an inverse multiplexing arrangement. A method includes generating a plurality of multilink segmentation and reassembly sublayer cells (700) at a first location, distributing the plurality of multilink segmentation and reassembly sublayer cells (700) across a plurality of virtual circuits (802); transmitting the plurality of multilink segmentation and reassembly sublayer cells to a second location via the plurality of virtual circuits (802); and receiving the plurality of multilink segmentation and reassembly sublayer cells (700) at the second location. An apparatus includes a multilink segmentation and reassembly sublayer transmitter, including: a source buffer (900); a multilink controller (902) coupled to the source buffer (900); and a plurality of virtual circuits (903) coupled to the multilink controller (902).
摘要翻译：描述了用于以反向多路复用布置的多重虚拟电路（802）的多链路分段和重组的系统和方法。一种方法包括在第一位置产生多个多链路分段和重组子层小区（700），以跨多个虚拟电路（802）分发多个多链路分段和重组子层小区（700）; 通过所述多个虚拟电路将所述多个多链路分段和重组子层小区发送到第二位置; 以及在所述第二位置处接收所述多个多链路分段和重组子层小区（700）。一种装置包括多链路分段和重组子层发射机，包括：源缓冲器（900）; 耦合到源缓冲器（900）的多链路控制器（902）; 以及耦合到所述多链路控制器（902）的多个虚拟电路（903）。

4. 发明申请

WO0173954A3 ASYMMETRIC DIGITAL SUBSCRIBER LINE METHODS SUITABLE FOR LONG SUBSCRIBER LOOPS 审中-公开
标题翻译：不适当的数字订阅方式适用于长期订阅者
公开(公告)号：WO0173954A3
公开(公告)日：2002-01-03
申请号：PCT/US0110734
申请日：2001-03-29
申请人： SYMMETRICOM INC , SHENOI KISHAN , SQUADRITO SANDRO , BOGARDUS GARY
发明人： SHENOI KISHAN , SQUADRITO SANDRO , BOGARDUS GARY
IPC分类号： H04L5/02 , H04L5/14 , H04L25/22 , H04L27/26 , H04L25/20
CPC分类号： H04L5/143 , H04L5/023 , H04L25/22 , H04L27/264 , H04L27/2653
摘要： Systems, methods and apparatus for asymmetric digital subscriber loops, including a modulator for transmitting a first communication, in a first direction over a transmission medium, the modulator operably coupled to a first amplification interface for providing a first gain adjustment, based on a first attenuation of the first communication in the first direction by a first direction impedance of the transmission medium; and a demodulator operably coupled to the modulator, for receiving a second communication, in a second direction over the transmission medium, the demodulator operably coupled to a second amplification interface for providing a second gain adjustment, based on a second attenuation of the second communication in the second direction by a second direction impedance of the transmission medium.
摘要翻译：用于非对称数字用户环路的系统，方法和装置，包括用于在传输介质上沿第一方向传输第一通信的调制器，所述调制器可操作地耦合到第一放大接口，用于基于第一衰减提供第一增益调整通过传输介质的第一方向阻抗在第一方向上进行第一通信; 以及解调器，其可操作地耦合到所述调制器，用于在所述传输介质上的第二方向上接收第二通信，所述解调器可操作地耦合到第二放大接口，用于基于所述第二通信的第二通信的第二衰减来提供第二增益调整第二方向是传输介质的第二方向阻抗。

5. 发明申请

WO2008103170A1 ASSISTED WALL-CLOCK 审中-公开
标题翻译：辅助墙壁时钟
公开(公告)号：WO2008103170A1
公开(公告)日：2008-08-28
申请号：PCT/US2007/062452
申请日：2007-02-20
申请人： SYMMETRICOM, INC. , SHENOI, Kishan , ZAMPETTI, George, P.
发明人： SHENOI, Kishan , ZAMPETTI, George, P.
IPC分类号： H04J3/06
CPC分类号： H04L12/413 , G06F1/14 , H04J3/0664 , H04J3/0667
摘要： One embodiment of the present invention sets forth a method for extracting a frequency reference carried in the physical layer of the incoming signal, using it to stabilize the local oscillator, and generating a suitable estimate of the clock correction to obtain an accurate time-of-day information from the client wall-clock of a computing device. The enhanced Jam-Sync method includes the steps of performing iterations to derive the estimates of the time offset between the true time-of-day and the System Time Clock (STC) in the forward and reverse directions of data transmission and calculating an estimate of the overall clock correction value. With these steps, the negative effects of packet delay variation may be mitigated and a value necessary for correcting the STC within the client wall-clock is determined. Consequently, quality control of the client wall-clock is achieved at significantly reduced cost and decreased level of complexity relative to the prior art approaches.
摘要翻译：本发明的一个实施例提出了一种用于提取输入信号的物理层中承载的频率参考的方法，使用它来稳定本地振荡器，并且产生适当的时钟校正估计以获得准确的时间 - 来自计算设备的客户端时钟的日间信息。增强的Jam-Sync方法包括以下步骤：执行迭代以得出数据传输的正向和反向方向上的真实时间与系统时间时钟（STC）之间的时间偏移的估计，并且计算估计值整体时钟校正值。通过这些步骤，可以减轻分组延迟变化的负面影响，并且确定用于校正客户端挂钟内的STC所需的值。因此，相对于现有技术的方法，以显着降低的成本和降低的复杂程度来实现客户端时钟的质量控制。

6. 发明申请

WO2013048770A1 SYSTEMS AND METHODS UTILIZING RANDOMIZED CLOCK RATES TO REDUCE SYSTEMATIC TIME-STAMP GRANULARITY ERRORS IN NETWORK PACKET COMMUNICATIONS 审中-公开
标题翻译：系统和方法利用随机时钟频率来降低网络分组通信中的系统时间戳错误错误
公开(公告)号：WO2013048770A1
公开(公告)日：2013-04-04
申请号：PCT/US2012/055300
申请日：2012-09-14
申请人： ANUE SYSTEMS, INC. , WEBB III, Charles A. , SHENOI, Kishan
发明人： WEBB III, Charles A. , SHENOI, Kishan
IPC分类号： G06F1/12
CPC分类号： H04J3/0697 , H03L7/16 , H03L7/1974 , H04J3/0661 , H04J3/0667
摘要： Systems and methods are disclosed for utilizing slave (receive) time-stamp clock rates different from master (sender) time-stamp clock rates to randomize and thereby reduce systematic time-stamp granularity errors in network packet communications. The slave (receive) time-stamp clock rate for some embodiments is set to a fixed value having a relationship with the master (sender) time-stamp clock rate such that the ratio of the slave (receive) clock rate to the master (sender) clock rate is a rational number. Other embodiments use a time-varying frequency for the slave (receive) time-stamp clock rate to randomize the slave (receive) time-stamp clock with respect to the master (sender) time-stamp clock. Additional variations can also be implemented.
摘要翻译：公开了利用与主（发送者）时间戳时钟速率不同的从（接收）时间标记时钟速率来随机化并由此减少网络分组通信中的系统时间戳粒度错误的系统和方法。一些实施例的从属（接收）时间戳时钟速率被设置为与主（发送器）时间戳时钟速率具有关系的固定值，使得从（接收）时钟速率与主机（发送器）的比率）时钟频率是一个理性数字。其他实施例使用从属（接收）时间戳时钟速率的时变频率来相对于主（发送者）时间戳时钟随机化从（接收）时间戳时钟。还可以实现其他变型。

7. 发明申请

WO0177705A3 GLOBAL POSITIONING SYSTEM RECEIVER CAPABLE OF FUNCTIONING IN THE PRESENCE OF INTERFERENCE 审中-公开
标题翻译：全球定位系统接收机可以在干扰存在的情况下进行功能化
公开(公告)号：WO0177705A3
公开(公告)日：2002-07-04
申请号：PCT/US0111431
申请日：2001-04-04
申请人： SYMMETRICOM INC , SHENOI KISHAN , HEINZL JOHANN , JACOBSEN GARY , YANG JINING
发明人： SHENOI KISHAN , HEINZL JOHANN , JACOBSEN GARY , YANG JINING
IPC分类号： G01S1/00 , H03J1/00 , H03J3/08 , G01S1/02 , G01S1/04 , H04B1/707
CPC分类号： G01S19/37 , G01S19/21 , H03J1/0008 , H03J3/08 , H04B1/7102
摘要： Systems and methods are described for a GPS receiver capable of functioning in the presence of interference. A method includes detecting an interfering signal including: tuning a band pass filter over a frequency range; and at each of a plurality of incremental frequencies; computing a set of band pass filter coefficients; sending the set of band pass filter coefficients to a digital filter; repeatedly transforming an analog-to-digital converter output having a quantization level in excess of 2 bits into a band pass filter output with the digital filter to obtain a plurality of samples; computing an average of the plurality of samples; and comparing the average to a threshold to detect peaks that exceed a threshold. An apparatus, comprising: an analog radio frequency circuit; an analog-to-digital converter coupled to the analog radio frequency circuit, the analog-to-digital converter providing a quantization level in excess of 2 bits; a digital filter coupled to the analog-to-digital converter; and a digital circuit coupled to the digital filter.
摘要翻译：为能够在存在干扰的情况下起作用的GPS接收机描述系统和方法。一种方法包括检测干扰信号，包括：在频率范围上调谐带通滤波器; 并且在多个增量频率中的每一个处; 计算一组带通滤波器系数; 将一组带通滤波器系数发送到数字滤波器; 将具有超过2位的量化级的模数转换器输出反复变换为与数字滤波器一起输出的带通滤波器，以获得多个采样; 计算所述多个样本的平均值; 并将平均值与阈值进行比较以检测超过阈值的峰值。一种装置，包括：模拟射频电路; 耦合到所述模拟射频电路的模数转换器，所述模数转换器提供超过2位的量化级; 耦合到所述模数转换器的数字滤波器; 以及耦合到数字滤波器的数字电路。

8. 发明申请

WO0150727A3 DIGITAL SUBSCRIBER LOOP REPEATERS AND ASSOCIATED METHODS 审中-公开
标题翻译：数字订阅者循环重复和相关方法
公开(公告)号：WO0150727A3
公开(公告)日：2001-12-13
申请号：PCT/US0035714
申请日：2000-12-28
申请人： SYMMETRICOM INC , SHENOI KISHAN
发明人： SHENOI KISHAN
IPC分类号： H04M19/00 , H04L25/20
CPC分类号： H04M19/006
摘要： Systems and methods are described for digital subscriber loop repeaters. A method of transforming a digital subscriber loop signal includes providing the digital subscriber loop signal; and increasing a gain of the digital subscriber loop signal with a digital subscriber loop repeater. The systems and methods provide advantages because DSL can be provided over long loops and/or over coil loaded loops.
摘要翻译：为数字用户环路中继器描述了系统和方法。一种变换数字用户环路信号的方法包括提供数字用户环路信号; 并用数字用户环路中继器增加数字用户环路信号的增益。系统和方法提供了优点，因为DSL可以在长环路和/或线圈负载环路上提供。

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