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    • 3. 发明申请
    • MAPPING BETWEEN REGISTERS USED BY MULTIPLE INSTRUCTION SETS
    • 由多个指令集使用的寄存器之间的映射
    • WO2011114121A1
    • 2011-09-22
    • PCT/GB2011/050306
    • 2011-02-16
    • ARM LIMITEDGRISENTHWAITE, Richard, RoySEAL, David, James
    • GRISENTHWAITE, Richard, RoySEAL, David, James
    • G06F9/30G06F9/318G06F9/38
    • G06F9/30112G06F9/30123G06F9/30138G06F9/30174G06F9/30189G06F9/30196G06F9/384G06F9/3863
    • A processor (4) is provided which supports a first instruction set specifying 32-bit architectural registers and a second instruction set specifying 64-bit architectural registers. Each of these instruction sets is presented with its own set of architectural registers for use. The first set of registers presented to the first instruction set has a one-to-one mapping to the second set of registers presented to this second instruction set. The registers which are provided in hardware are 64-bit registers. In some embodiments, when executing program instructions of the first instruction set, only the least significant portion of these 64-bit registers are accessed and manipulated with the remaining most significant portion of the registers being left unaltered. Register specifying fields within instructions of the first instruction set are decoded together with a current exception mode to determine which architectural register to use whereas the second instruction set uses register specifying fields without a dependence upon exception mode to determine which architectural register are to be used.
    • 提供了一种处理器(4),其支持指定32位架构寄存器的第一指令集和指定64位架构寄存器的第二指令集。 这些指令集中的每一个都带有自己的一组架构寄存器供使用。 呈现给第一指令集的第一组寄存器具有与呈现给该第二指令集的第二组寄存器的一对一映射。 在硬件中提供的寄存器是64位寄存器。 在一些实施例中,当执行第一指令集的程序指令时,只有这些64位寄存器的最低有效部分被访问和操作,其中最重要的寄存器部分保持不变。 在第一指令集的指令内的寄存器指定字段与当前异常模式一起被解码以确定要使用的架构寄存器,而第二指令集使用寄存器指定字段而不依赖于异常模式来确定要使用哪个架构寄存器。
    • 8. 发明申请
    • OPERAND SIZE CONTROL
    • 操作尺寸控制
    • WO2011114125A1
    • 2011-09-22
    • PCT/GB2011/050397
    • 2011-03-01
    • ARM LIMITEDGRISENTHWAITE, Richard, RoySEAL, David, JamesRAPHALEN, Philippe, Jean-PierreSMITH, Lee, Douglas
    • GRISENTHWAITE, Richard, RoySEAL, David, JamesRAPHALEN, Philippe, Jean-PierreSMITH, Lee, Douglas
    • G06F9/30G06F9/312G06F1/32G06F21/00
    • G06F9/3016G06F9/3001G06F9/30112G06F9/3861G06F21/577G06F21/70G06F2221/2145
    • A data processing system (2) is provided with processing circuitry (8,10,12) as well as a bank of 64-bit registers (6). An instruction decoder (14) decodes arithmetic instructions and logical instruction specifying arithmetic operations and logical operations to be performed upon operands stored within the 64-bit registers (6). The instruction decoder (14) is responsive to an operand size field SF within the arithmetic instructions and the logical instructions specifying whether the operands are 64-bit operands or 32-bit operands. Each 64-bit register stores either a single 64-bit operand or a single 32-bit operand. For a given arithmetic instruction and logical instruction either all of the operands are 64-bit operands or all of the operands are 32-bit operands. A plurality of exception levels arranged in a hierarchy of exception levels may be supported. If a switch is made to a lower exception level, then a check is made as to whether or not a register being used was previously subject to a 64-bit write to that register. If such a 64-bit write had previously taken place to that register, then the upper 32-bits are flushed so as to avoid data leakage from the higher exception level.
    • 数据处理系统(2)具有处理电路(8,10,12)以及一组64位寄存器(6)。 指令解码器(14)对存储在64位寄存器(6)中的操作数执行的运算指令和指定算术运算和逻辑运算的逻辑指令进行解码。 指令解码器(14)响应于算术指令内的操作数大小字段SF,以及指定操作数是64位操作数还是32位操作数的逻辑指令。 每个64位寄存器存储单个64位操作数或单个32位操作数。 对于给定的算术指令和逻辑指令,所有操作数都是64位操作数,或者所有操作数都是32位操作数。 可以支持以异常级别分层布置的多个异常级别。 如果将交换机设置为较低的异常级别,则检查所使用的寄存器是否先前对该寄存器进行64位写操作。 如果先前对该寄存器进行了这样的64位写操作,则高位32位被刷新,以避免数据从较高异常级别泄漏。
    • 9. 发明申请
    • A DATA PROCESSING APPARATUS AND METHOD FOR HANDLING PROCEDURE CALL INSTRUCTIONS
    • 一种数据处理装置和处理程序呼叫指令的方法
    • WO2007048988A1
    • 2007-05-03
    • PCT/GB2005/004131
    • 2005-10-26
    • ARM LIMITEDSEAL, David, James
    • SEAL, David, James
    • G06F9/38G06F9/42G06F9/30G06F9/46
    • G06F9/30101G06F9/322G06F9/3804G06F9/381
    • A data processing apparatus and method are provided for handling procedure call instructions. The data processing apparatus has processing logic for performing data processing operations specified by program instructions fetched from a sequence of addresses, at least one of the program instructions being a procedure call instruction specifying a branch operation to be performed. Further, a control value is stored within control storage, and the processing logic is operable in response to a control value modifying instruction to modify that control value. If the control value is clear, the processing logic is operable in response to the procedure call instruction to generate a return address value in addition to performing the branch operation, whereas if the control value is set, the processing logic is operable in response to the procedure call instruction to suppress generation of the return address value and to cause the control value to be clear in addition to performing the branch operation. This provides significant flexibility in how procedure call instructions are used within the data processing apparatus.
    • 提供了一种用于处理过程调用指令的数据处理装置和方法。 数据处理装置具有用于执行由地址序列取出的程序指令指定的数据处理操作的处理逻辑,程序指令中的至少一个是指定要执行的分支操作的过程调用指令。 此外,控制值存储在控制存储器中,并且处理逻辑可响应于控制值修改指令而操作以修改该控制值。 如果控制值清楚,则除了执行分支操作之外,响应于过程调用指令也可以处理逻辑以产生返回地址值,而如果设置了控制值,则处理逻辑可响应于 过程调用指令,以抑制返回地址值的生成,并且除了执行分支操作之外还使控制值清除。 这在数据处理设备中如何使用过程调用指令提供了显着的灵活性。