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    • 1. 发明申请
    • ENCODER AND ENCODING METHOD PROVIDING INCREMENTAL REDUNDANCY
    • 提供增量冗余的编码器和编码方法
    • WO2011104182A3
    • 2011-11-17
    • PCT/EP2011052417
    • 2011-02-18
    • SONY CORPSONY DEUTSCHLAND GMBHMUHAMMAD NABILSTADELMEIER LOTHARROBERT JOERGATUNGSIRI SAMUEL ASANGBENGYAMAMOTO MAKIKOSHINOHARA YUJISAKAI LUIYOKOKAWA TAKASHI
    • MUHAMMAD NABILSTADELMEIER LOTHARROBERT JOERGATUNGSIRI SAMUEL ASANGBENGYAMAMOTO MAKIKOSHINOHARA YUJISAKAI LUIYOKOKAWA TAKASHI
    • H03M13/11H04L1/00
    • H03M13/11H03M13/1165H03M13/3761H03M13/6519H04L1/0036H04L1/0045H04L1/0057H04L1/0059H04L1/0068H04L1/0083H04L2001/0098
    • The present invention relates to an encoder for error correction code encoding input data words (D) into codewords (Z1, Z2), comprising: an encoder input (1451) for receiving input data words (D) each comprising a first number K ldpc of information symbols, an encoding means (1452) for encoding an input data word (D) into a codeword (Z1, Z2, Z3, Z4) such that a codeword comprises a basic codeword portion (B) including a data portion (D) and a basic parity portion (Pb) of a second number N ldpc - K ldpc of basic parity symbols, and an auxiliary codeword portion (A) including an auxiliary parity portion (Pa) of a third number M IR of auxiliary parity symbols, wherein said encoding means (14) is adapted i) for generating said basic codeword portion (B) from an input data word (D) according to a first code, wherein a basic parity symbol is generated by accumulating an information symbol at a parity symbol address determined according to a first address generation rule, and ii) for generating said auxiliary codeword portion (A) from an input data word (D) according to a second code, wherein an auxiliary parity symbol is generated by accumulating an information symbol m at a parity symbol address ?, wherein said parity symbol addresses ? are determined according to a second address generation rule N ldpc - K ldpc + {x + m mod G a x Q IR } mod M IR if x > N ldpc - K ldpc ' wherein x denotes the addresses of a parity symbol accumulator corresponding to the first information symbol of a group of size Ga and Q IR is an auxiliary code rate dependent, predefined constant, and an encoder output (1454) for outputting said codewords (Z1, Z2).
    • 本发明涉及一种用于将输入数据字(D)编码为码字(Z1,Z2)的编码器,包括:编码器输入(1451),用于接收输入数据字(D),每个输入数据字包括第一数目K ldpc 信息符号;编码装置(1452),用于将输入数据字(D)编码为码字(Z1,Z2,Z3,Z4),使得码字包括包含数据部分(D)的基本码字部分(B);以及 基本奇偶校验码元的第二数量N ldpc -K ldpc的基本奇偶校验部分(Pb)以及包括辅助奇偶校验码元的第三数目M IR的辅助奇偶部分(Pa)的辅助码字部分(A),其中所述 编码装置(14)适于:i)根据第一码从输入数据字(D)产生所述基本码字部分(B),其中通过在确定的奇偶校验符号地址处累积信息符号来产生基本奇偶校验符号 根据第一个地址生成规则,以及ii)用于生成 根据第二代码从输入数据字(D)中除去所述辅助码字部分(A),其中辅助奇偶校验符号通过在奇偶校验符号地址β处累积信息符号m而产生, 根据第二地址生成规则N ldpc -K ldpc + {x + m mod G ax Q IR} mod M IR确定,如果x> N ldpc -K ldpc',其中x表示与所述第一地址生成规则相对应的奇偶符号累加器的地址 尺寸Ga和Q IR组的第一个信息符号是一个辅助码率相关的预定义常数,和一个用于输出所述码字(Z1,Z2)的编码器输出(1454)。
    • 2. 发明申请
    • ENCODER AND ENCODING METHOD PROVIDING INCREMENTAL REDUNDANCY
    • 编码和编码方法提供增值冗余
    • WO2011104182A2
    • 2011-09-01
    • PCT/EP2011/052417
    • 2011-02-18
    • SONY CORPORATIONSONY DEUTSCHLAND GMBHMUHAMMAD, NabilSTADELMEIER, LotharROBERT, JoergATUNGSIRI, Samuel AsangbengYAMAMOTO, MakikoSHINOHARA, YujiSAKAI, LuiYOKOKAWA, Takashi
    • MUHAMMAD, NabilSTADELMEIER, LotharROBERT, JoergATUNGSIRI, Samuel AsangbengYAMAMOTO, MakikoSHINOHARA, YujiSAKAI, LuiYOKOKAWA, Takashi
    • H03M13/11H03M13/1165H03M13/3761H03M13/6519H04L1/0036H04L1/0045H04L1/0057H04L1/0059H04L1/0068H04L1/0083H04L2001/0098
    • The present invention relates to an encoder for error correction code encoding input data words (D) into codewords (Z1, Z2), comprising: an encoder input (1451) for receiving input data words (D) each comprising a first number K ldpc of information symbols, an encoding means (1452) for encoding an input data word (D) into a codeword (Z1, Z2, Z3, Z4) such that a codeword comprises a basic codeword portion (B) including a data portion (D) and a basic parity portion (Pb) of a second number N ldpc - K ldpc of basic parity symbols, and an auxiliary codeword portion (A) including an auxiliary parity portion (Pa) of a third number M IR of auxiliary parity symbols, wherein said encoding means (14) is adapted i) for generating said basic codeword portion (B) from an input data word (D) according to a first code, wherein a basic parity symbol is generated by accumulating an information symbol at a parity symbol address determined according to a first address generation rule, and ii) for generating said auxiliary codeword portion (A) from an input data word (D) according to a second code, wherein an auxiliary parity symbol is generated by accumulating an information symbol m at a parity symbol address γ , wherein said parity symbol addresses γ are determined according to a second address generation rule N ldpc - K ldpc + {x + m mod G a x Q IR } mod M IR if x > N ldpc - K ldpc ' wherein x denotes the addresses of a parity symbol accumulator corresponding to the first information symbol of a group of size G a and Q IR is an auxiliary code rate dependent, predefined constant, and an encoder output (1454) for outputting said codewords (Z1, Z2).
    • 本发明涉及用于将输入数据字(D)编码成码字(Z1,Z2)的纠错码的编码器,包括:编码器输入(1451),用于接收输入数据字(D),每个包括第一数字K ldpc 信息符号,用于将输入数据字(D)编码成码字(Z1,Z2,Z3,Z4)的编码装置(1452),使得码字包括包括数据部分(D)的基本码字部分(B)和 基本奇偶校验符号的第二数量N lpc-K ldpc的基本奇偶校验部分(Pb)和包括辅助奇偶校验符号的第三号码M IR的辅助奇偶校验部分(Pa)的辅助码字部分(A),其中所述 编码装置(14)适于:i)根据第一代码从输入数据字(D)产生所述基本码字部分(B),其中通过在确定的奇偶校验符号地址处累积信息符号来产生基本奇偶校验符号 根据第一个地址生成规则,和ii)代表 根据第二代码从输入数据字(D)中删除所述辅助码字部分(A),其中通过在奇偶校验符号地址α处累积信息符号m来产生辅助奇偶校验符号,其中所述奇偶校验符号地址 根据第二地址生成规则N ldpc -K ldpc + {x + m mod G ax Q IR} mod M IR确定,如果x> N ldpc -K ldpc'其中x表示对应于奇偶校验符号累加器的地址 大小为Ga和Q IR的组的第一信息符号是辅助码率依赖的预定常数,以及用于输出所述码字(Z1,Z2)的编码器输出(1454)。