专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20130026602A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20130026602A1
公开(公告)日：2013-01-31
申请号：US13592910
申请日：2012-08-23
申请人： Ryuichi OKAMURA
发明人： Ryuichi OKAMURA
IPC分类号： H01L29/92
CPC分类号： H01L24/10 , H01L23/5223 , H01L24/05 , H01L24/13 , H01L2224/02166 , H01L2224/0401 , H01L2224/04042 , H01L2224/05556 , H01L2224/13 , H01L2224/13099 , H01L2224/48463 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01022 , H01L2924/01029 , H01L2924/01033 , H01L2924/0104 , H01L2924/01042 , H01L2924/01047 , H01L2924/01065 , H01L2924/01072 , H01L2924/01073 , H01L2924/01074 , H01L2924/01075 , H01L2924/01082 , H01L2924/014 , H01L2924/04941 , H01L2924/04953 , H01L2924/19041 , H01L2924/30105 , H01L2924/3011 , H01L2924/00
摘要： A semiconductor device, which exhibits an increased design flexibility for a capacitor element, and can be manufactured with simple method, is provided. A semiconductor device 100 includes: a silicon substrate 101; an interlayer film 103 provided on the silicon substrate 101; a multiple-layered interconnect embedded in the interlayer film 103; a flip-chip pad 111, provided so as to be opposite to an upper surface of an uppermost layer interconnect 105 in the multiple-layered interconnect and having a solder ball 113 for an external coupling mounted thereon; and a capacitance film 109 provided between said uppermost layer interconnect 105 and the flip-chip pad 111. Such semiconductor device 100 includes the flip-chip pad 111 composed of an uppermost layer interconnect 105, a capacitive film 109 and a capacitor element 110.
摘要翻译：提供一种对电容器元件具有增加的设计灵活性并且可以用简单方法制造的半导体器件。半导体器件100包括：硅衬底101; 设置在硅基板101上的中间膜103; 嵌入在层间膜103中的多层互连; 倒装芯片焊盘111，设置成与多层互连中的最上层布线105的上表面相对，并且具有安装在其上的用于外部耦合的焊球113; 以及设置在所述最上层布线105和倒装芯片焊盘111之间的电容膜109.这种半导体装置100包括由最上层布线105，电容膜109和电容器元件110构成的倒装芯片焊盘111。

2. 发明授权

US08283753B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US08283753B2
公开(公告)日：2012-10-09
申请号：US11712910
申请日：2007-03-02
申请人： Ryuichi Okamura
发明人： Ryuichi Okamura
IPC分类号： H01L29/93
CPC分类号： H01L24/10 , H01L23/5223 , H01L24/05 , H01L24/13 , H01L2224/02166 , H01L2224/0401 , H01L2224/04042 , H01L2224/05556 , H01L2224/13 , H01L2224/13099 , H01L2224/48463 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01022 , H01L2924/01029 , H01L2924/01033 , H01L2924/0104 , H01L2924/01042 , H01L2924/01047 , H01L2924/01065 , H01L2924/01072 , H01L2924/01073 , H01L2924/01074 , H01L2924/01075 , H01L2924/01082 , H01L2924/014 , H01L2924/04941 , H01L2924/04953 , H01L2924/19041 , H01L2924/30105 , H01L2924/3011 , H01L2924/00
摘要： A semiconductor device, which exhibits an increased design flexibility for a capacitor element, and can be manufactured with simple method, is provided. A semiconductor device 100 includes: a silicon substrate 101; an interlayer film 103 provided on the silicon substrate 101; a multiple-layered interconnect embedded in the interlayer film 103; a flip-chip pad 111, provided so as to be opposite to an upper surface of an uppermost layer interconnect 105 in the multiple-layered interconnect and having a solder ball 113 for an external coupling mounted thereon; and a capacitance film 109 provided between said uppermost layer interconnect 105 and the flip-chip pad 111. Such semiconductor device 100 includes the flip-chip pad 111 composed of an uppermost layer interconnect 105, a capacitive film 109 and a capacitor element 110.
摘要翻译：提供一种对电容器元件具有增加的设计灵活性并且可以用简单方法制造的半导体器件。半导体器件100包括：硅衬底101; 设置在硅基板101上的中间膜103; 嵌入在层间膜103中的多层互连; 倒装芯片焊盘111，设置成与多层互连中的最上层布线105的上表面相对，并且具有安装在其上的用于外部耦合的焊球113; 以及设置在所述最上层布线105和倒装芯片焊盘111之间的电容膜109.这种半导体装置100包括由最上层布线105，电容膜109和电容器元件110构成的倒装芯片焊盘111。

3. 发明申请

US20110316052A1 SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 有权
标题翻译：半导体集成电路设备
公开(公告)号：US20110316052A1
公开(公告)日：2011-12-29
申请号：US13150842
申请日：2011-06-01
申请人： Hiroshi FURUTA , Takaaki KOBAYASHI , Hirofumi AZUHATA , Tomoya MORITA , Ryuichi OKAMURA , Toshifumi TAKAHASHI
发明人： Hiroshi FURUTA , Takaaki KOBAYASHI , Hirofumi AZUHATA , Tomoya MORITA , Ryuichi OKAMURA , Toshifumi TAKAHASHI
IPC分类号： H01L27/088
CPC分类号： H01L27/0207 , H01L27/11807
摘要： In addition to a memory macro region and functional circuit regions on a substrate, a semiconductor integrated circuit device includes a dummy pattern region 40 arranged between the functional circuit regions and between the memory macro region 10 and the functional circuit regions and including a dummy pattern. The dummy pattern has a pattern identical to that of diffusion layers and gate electrodes of a memory cell pattern in a memory cell array region. An area ratio of dummy diffusion layer(s) and dummy gate electrode(s) in the dummy pattern region is equal to or greater than that of the diffusion layers and the gate electrode(s) in the memory cell array region.
摘要翻译：除了存储器宏区域和基板上的功能电路区域之外，半导体集成电路器件还包括布置在功能电路区域之间以及存储器宏区域10和功能电路区域之间并包括虚拟图案的虚设图案区域40。虚设图案具有与存储单元阵列区域中的存储单元图案的扩散层和栅电极相同的图案。虚设图形区域中的虚设扩散层和伪栅电极的面积比等于或大于存储单元阵列区域中的扩散层和栅电极的面积比。

4. 发明授权

US5990522A Field effect transistor with improved source/drain diffusion regions having an extremely small capacitance 失效
公开(公告)号：US5990522A
公开(公告)日：1999-11-23
申请号：US34358
申请日：1998-03-04
申请人： Ryuichi Okamura
发明人： Ryuichi Okamura
IPC分类号： H01L29/78 , H01L21/265 , H01L21/336 , H01L21/8238 , H01L27/092 , H01L29/06 , H01L29/10 , H01L29/786 , H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113
CPC分类号： H01L29/66575 , H01L21/26513 , H01L29/0653 , H01L29/1083 , H01L29/6659 , H01L29/78654
摘要： The invention provides a diffusion region structure in a semiconductor device wherein the diffusion region is applied with alternating voltages in an operation of the semiconductor device. The structure comprises at least one diffusion region being doped with an impurity of a first conductivity type at a first impurity concentration and also being provided in a semiconductor bulk region doped with an impurity of a second conductivity type at a second impurity concentration lower than the first impurity concentration, and at least a diffusion capacitance reduction layer provided under the diffusion region so as to be in contact with a bottom of the diffusion region. The diffusion capacitance reduction layer may be doped with an impurity of the second conductivity type at a third impurity concentration which is at least lower than the second impurity concentration of the semiconductor bulk region and not lower than zero or may be mode of an insulating material to thereby reduce a capacitance of the diffusion region.

5. 发明申请

US20060219913A1 Length measurement pattern, semiconductor device, and method of manufacturing a semiconductor device 失效
标题翻译：长度测量图案，半导体器件和制造半导体器件的方法
公开(公告)号：US20060219913A1
公开(公告)日：2006-10-05
申请号：US11356121
申请日：2006-02-17
申请人： Ryuichi Okamura
发明人： Ryuichi Okamura
IPC分类号： G01N23/00
CPC分类号： G01D5/347 , G01D5/34707
摘要： A length measurement pattern is used for forming a contact and a via on a diffusion layer and on a lower layer interconnect, respectively, with a photoresist. The length measurement pattern includes a first pattern 16 serving as an object of length measurement in length measurement SEM and a second pattern 17 disposed to be spaced apart from the first pattern 16 and used for positioning and focusing of the length measurement SEM.
摘要翻译：使用长度测量图案分别在光致抗蚀剂上在扩散层和下层互连上形成接触和通孔。长度测量图案包括用作长度测量SEM中的长度测量对象的第一图案16和布置成与第一图案16间隔开并用于长度测量SEM的定位和聚焦的第二图案17。

6. 发明授权

US5975309A Fluidized-bed classifier 失效
标题翻译：流化床分级机
公开(公告)号：US5975309A
公开(公告)日：1999-11-02
申请号：US838141
申请日：1997-04-15
申请人： Yoshihiro Mitsuda , Seisuke Sawamura , Ryuichi Okamura , Hiroshi Ueda , Fuminori Ando , Kanzaburo Sutoh , Mitsuaki Murata , Tsutomu Hirobe
发明人： Yoshihiro Mitsuda , Seisuke Sawamura , Ryuichi Okamura , Hiroshi Ueda , Fuminori Ando , Kanzaburo Sutoh , Mitsuaki Murata , Tsutomu Hirobe
IPC分类号： B07B4/08 , B02C15/04 , B02C23/30 , B03B4/00 , B07B4/00
CPC分类号： B03B4/00
摘要： A fluidized-bed classifier has a vessel defining a space divided into an upper fluidized-bed chamber and a lower gas chamber by a perforated dispersion plate having the shape of a funnel. Rising currents of a gas, such as air, are blown through the dispersion plate into the upper fluidized-bed chamber to produce a fluidized bed of a particulate material over the dispersion plate. The lower gas chamber is divided into a first gas chamber and a second gas chamber by a partition plate. The gas is supplied into the first air chamber so that rising gas currents of a velocity necessary for fluidizing coarse particles contained in the particulate material fed into the vessel are blown from the first air chamber through the dispersion plate into the fluidized-bed chamber. The gas is supplied into the second air chamber so that rising gas currents of a velocity lower than the velocity of the rising gas currents blown from the first air chamber into the fluidized-bed chamber are blown into the fluidized-bed chamber so that coarse particles contained in the particulate material are not fluidized and does not flow together with fine particles into a fine particle discharge chute.
摘要翻译：流化床分级器具有通过具有漏斗形状的穿孔分散板限定划分为上流化床室和下气室的空间的容器。诸如空气的气体的上升流通过分散板吹入上流化床室，以在分散板上产生颗粒材料的流化床。下部气室通过隔板分为第一气室和第二气室。气体被供应到第一空气室中，使得流入容器中的颗粒物质中所含的粗颗粒流动所需的速度的上升气流从第一空气室通过分散板吹入流化床室。气体被供应到第二空气室中，使得低于从第一气室吹入流化床室的上升气流速度的速度的上升气流被吹入流化床室，使得粗颗粒颗粒材料中所含的颗粒物质不会流化，并且不会与细颗粒一起流入细颗粒排出槽。

7. 发明授权

US07420190B2 Length measurement pattern, semiconductor device, and method of manufacturing a semiconductor device 失效
标题翻译：长度测量图案，半导体器件和制造半导体器件的方法
公开(公告)号：US07420190B2
公开(公告)日：2008-09-02
申请号：US11356121
申请日：2006-02-17
申请人： Ryuichi Okamura
发明人： Ryuichi Okamura
IPC分类号： G01N23/00 , G03F9/00
CPC分类号： G01D5/347 , G01D5/34707
摘要： A length measurement pattern is used for forming a contact and a via on a diffusion layer and on a lower layer interconnect, respectively, with a photoresist. The length measurement pattern includes a first pattern 16 serving as an object of length measurement in length measurement SEM and a second pattern 17 disposed to be spaced apart from the first pattern 16 and used for positioning and focusing of the length measurement SEM.
摘要翻译：使用长度测量图案分别在光致抗蚀剂上在扩散层和下层互连上形成接触和通孔。长度测量图案包括用作长度测量SEM中的长度测量对象的第一图案16和布置成与第一图案16间隔开并用于长度测量SEM的定位和聚焦的第二图案17。

8. 发明申请

US20070216027A1 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US20070216027A1
公开(公告)日：2007-09-20
申请号：US11712910
申请日：2007-03-02
申请人： Ryuichi Okamura
发明人： Ryuichi Okamura
IPC分类号： H01L23/48
CPC分类号： H01L24/10 , H01L23/5223 , H01L24/05 , H01L24/13 , H01L2224/02166 , H01L2224/0401 , H01L2224/04042 , H01L2224/05556 , H01L2224/13 , H01L2224/13099 , H01L2224/48463 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01022 , H01L2924/01029 , H01L2924/01033 , H01L2924/0104 , H01L2924/01042 , H01L2924/01047 , H01L2924/01065 , H01L2924/01072 , H01L2924/01073 , H01L2924/01074 , H01L2924/01075 , H01L2924/01082 , H01L2924/014 , H01L2924/04941 , H01L2924/04953 , H01L2924/19041 , H01L2924/30105 , H01L2924/3011 , H01L2924/00
摘要： A semiconductor device, which exhibits an increased design flexibility for a capacitor element, and can be manufactured with simple method, is provided. A semiconductor device 100 includes: a silicon substrate 101; an interlayer film 103 provided on the silicon substrate 101; a multiple-layered interconnect embedded in the interlayer film 103; a flip-chip pad 111, provided so as to be opposite to an upper surface of an uppermost layer interconnect 105 in the multiple-layered interconnect and having a solder ball 113 for an external coupling mounted thereon; and a capacitance film 109 provided between said uppermost layer interconnect 105 and the flip-chip pad 111. Such semiconductor device 100 includes the flip-chip pad 111 composed of an uppermost layer interconnect 105, a capacitive film 109 and a capacitor element 110.
摘要翻译：提供一种对电容器元件具有增加的设计灵活性并且可以用简单方法制造的半导体器件。半导体器件100包括：硅衬底101; 设置在硅基板101上的中间膜103; 嵌入在层间膜103中的多层互连; 倒装芯片焊盘111，设置成与多层互连中的最上层布线105的上表面相对，并且具有安装在其上的用于外部耦合的焊球113; 以及设置在所述最上层布线105和倒装芯片焊盘111之间的电容膜109.这种半导体装置100包括由最上层布线105，电容膜109和电容器元件110构成的倒装芯片焊盘111。

9. 发明授权

US08575721B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US08575721B2
公开(公告)日：2013-11-05
申请号：US13592910
申请日：2012-08-23
申请人： Ryuichi Okamura
发明人： Ryuichi Okamura
IPC分类号： H01L21/02 , H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L24/10 , H01L23/5223 , H01L24/05 , H01L24/13 , H01L2224/02166 , H01L2224/0401 , H01L2224/04042 , H01L2224/05556 , H01L2224/13 , H01L2224/13099 , H01L2224/48463 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01022 , H01L2924/01029 , H01L2924/01033 , H01L2924/0104 , H01L2924/01042 , H01L2924/01047 , H01L2924/01065 , H01L2924/01072 , H01L2924/01073 , H01L2924/01074 , H01L2924/01075 , H01L2924/01082 , H01L2924/014 , H01L2924/04941 , H01L2924/04953 , H01L2924/19041 , H01L2924/30105 , H01L2924/3011 , H01L2924/00
摘要： A semiconductor device, which exhibits an increased design flexibility for a capacitor element, and can be manufactured with simple method, is provided. A semiconductor device 100 includes: a silicon substrate 101; an interlayer film 103 provided on the silicon substrate 101; a multiple-layered interconnect embedded in the interlayer film 103; a flip-chip pad 111, provided so as to be opposite to an upper surface of an uppermost layer interconnect 105 in the multiple-layered interconnect and having a solder ball 113 for an external coupling mounted thereon; and a capacitance film 109 provided between said uppermost layer interconnect 105 and the flip-chip pad 111. Such semiconductor device 100 includes the flip-chip pad 111 composed of an uppermost layer interconnect 105, a capacitive film 109 and a capacitor element 110.
摘要翻译：提供一种对电容器元件具有增加的设计灵活性并且可以用简单方法制造的半导体器件。半导体器件100包括：硅衬底101; 设置在硅基板101上的中间膜103; 嵌入在层间膜103中的多层互连; 倒装芯片焊盘111，设置成与多层互连中的最上层布线105的上表面相对，并且具有安装在其上的用于外部耦合的焊球113; 以及设置在所述最上层布线105和倒装芯片焊盘111之间的电容膜109.这种半导体装置100包括由最上层布线105，电容膜109和电容器元件110构成的倒装芯片焊盘111。

10. 发明申请

US20060163748A1 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US20060163748A1
公开(公告)日：2006-07-27
申请号：US11325482
申请日：2006-01-05
申请人： Masatoshi Watarai , Ryuichi Okamura
发明人： Masatoshi Watarai , Ryuichi Okamura
IPC分类号： H01L23/48
CPC分类号： H01L22/24 , H01L22/34
摘要： The semiconductor device includes a semiconductor substrate, a diffusion layer, an interconnect layer, a contact plug, a contact-inspection hole, a via plug, and a via-inspection hole. Similarly to a contact plug hole, the contact-inspection hole extends from the diffusion layer to the interconnect layer. The opening of the contact-inspection hole on the side of the diffusion layer is disposed across the boundary of the diffusion layer. Also, similarly to a via plug hole, the via-inspection hole extends from an interconnect to an interconnect layer. The opening of the via-inspection hole on the side of the interconnect is disposed across the boundary of the interconnect.
摘要翻译：半导体器件包括半导体衬底，扩散层，互连层，接触插塞，接触检查孔，通孔插头和通孔检查孔。类似于接触塞孔，接触检查孔从扩散层延伸到互连层。扩散层一侧的接触检查孔的开口设置在扩散层的边界的两侧。此外，与通孔塞孔类似，通孔检查孔从互连件延伸到互连层。互连侧面的通孔检查孔的开口跨越互连的边界设置。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式