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1. 发明授权

US07199676B2 Frequency adjustment circuit 有权
标题翻译：频率调节电路
公开(公告)号：US07199676B2
公开(公告)日：2007-04-03
申请号：US11196512
申请日：2005-08-04
申请人： Tetsuya Tokunaga , Hiroyuki Arai , Takeshi Kimura , Ryouichi Ando , Mamoru Yamaguchi
发明人： Tetsuya Tokunaga , Hiroyuki Arai , Takeshi Kimura , Ryouichi Ando , Mamoru Yamaguchi
IPC分类号： H03K3/02
CPC分类号： H03K3/0231 , H03K2005/00084
摘要： A frequency adjustment circuit that maintains a target frequency even when frequency adjustment data of zapping circuit is changed by an external noise is offered. The frequency adjustment circuit includes a reset signal generation circuit, a frequency adjustment data latch circuit that latches and retains the frequency adjustment data ZP1 and ZP2 generated by a first zapping circuit and a second zapping circuit based on a latch clock ZCLK and a latch clock generation circuit that generates the latch clock ZCLK. The reset signal generation circuit generates a periodic reset signal ZRES that is synchronized with a rise of an enable signal EN generated from an interface circuit. The latch clock generation circuit generates the latch clock ZCLK that is synchronized with a fall of the enable signal EN.
摘要翻译：提供即使在由于外部噪声而使切换电路的频率调整数据变化的情况下也能够维持目标频率的频率调整电路。频率调整电路包括复位信号生成电路，频率调整数据锁存电路，其锁存并保持由第一切换电路产生的频率调整数据ZP 1和ZP 2，以及基于锁存时钟ZCLK和锁存器的第二切换电路时钟生成电路，生成锁存时钟ZCLK。复位信号产生电路产生与从接口电路产生的使能信号EN的上升同步的周期性复位信号ZRES。锁存时钟产生电路产生与使能信号EN的下降同步的锁存时钟ZCLK。

2. 发明申请

US20060033583A1 Frequency adjustment circuit 有权
标题翻译：频率调节电路
公开(公告)号：US20060033583A1
公开(公告)日：2006-02-16
申请号：US11196512
申请日：2005-08-04
申请人： Tetsuya Tokunaga , Hiroyuki Arai , Takeshi Kimura , Ryouichi Ando , Mamoru Yamaguchi
发明人： Tetsuya Tokunaga , Hiroyuki Arai , Takeshi Kimura , Ryouichi Ando , Mamoru Yamaguchi
IPC分类号： H03L7/00
CPC分类号： H03K3/0231 , H03K2005/00084
摘要： A frequency adjustment circuit that maintains a target frequency even when frequency adjustment data of zapping circuit is changed by an external noise is offered. The frequency adjustment circuit includes a reset signal generation circuit, a frequency adjustment data latch circuit that latches and retains the frequency adjustment data ZP1 and ZP2 generated by a first zapping circuit and a second zapping circuit based on a latch clock ZCLK and a latch clock generation circuit that generates the latch clock ZCLK. The reset signal generation circuit generates a periodic reset signal ZRES that is synchronized with a rise of an enable signal EN generated from an interface circuit. The latch clock generation circuit generates the latch clock ZCLK that is synchronized with a fall of the enable signal EN.
摘要翻译：提供即使在由于外部噪声而使切换电路的频率调整数据变化的情况下也能够维持目标频率的频率调整电路。频率调整电路包括复位信号生成电路，频率调整数据锁存电路，其锁存并保持由第一切换电路产生的频率调整数据ZP 1和ZP 2，以及基于锁存时钟ZCLK和锁存器的第二切换电路时钟生成电路，生成锁存时钟ZCLK。复位信号产生电路产生与从接口电路产生的使能信号EN的上升同步的周期性复位信号ZRES。锁存时钟产生电路产生与使能信号EN的下降同步的锁存时钟ZCLK。

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