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1. 发明授权

US07127589B2 Data processor 有权
标题翻译：数据处理器
公开(公告)号：US07127589B2
公开(公告)日：2006-10-24
申请号：US10952913
申请日：2004-09-30
申请人： Hiroaki Nishikawa , Hiroshi Tomiyasu , Ryosuke Kurebayashi , Shinya Ito , Shouhei Nomoto
发明人： Hiroaki Nishikawa , Hiroshi Tomiyasu , Ryosuke Kurebayashi , Shinya Ito , Shouhei Nomoto
IPC分类号： G06F15/82 , G06F9/38
CPC分类号： G06F9/3836 , G06F9/3838 , G06F9/384 , G06F9/3857
摘要： A data processor capable of executing sequential processing efficiently while retaining the advantages of a prior art data-driven processor. The data processor includes: an instruction fetch unit which fetches a data-driven instruction or a control-driven instruction from an instruction memory based on an input packet or a program counter; an instruction decode unit which decodes the issued instruction and, in the case of the control-driven instruction, thereafter accesses a register and performs register renaming if a data hazard is detected; a firing control unit which stores the decoded instruction in a matching memory to wait therein, and which selects one of the ready-to-fire instructions and fires the selected instruction; an execution unit which performs an operation specified by the fired instruction and, in the case of the data-driven instruction, transfers an operation result to the instruction fetch unit, or in the case of the control-driven instruction, forwards the operation result to the firing control unit; and a write back unit which writes the operation result to a register.
摘要翻译：能够有效执行顺序处理的数据处理器，同时保持现有技术的数据驱动处理器的优点。数据处理器包括：指令提取单元，其基于输入分组或程序计数器从指令存储器取出数据驱动指令或控制驱动指令; 指令解码单元，其对所发出的指令进行解码，并且在控制驱动指令的情况下，如果检测到数据危险，则访问寄存器并执行寄存器重命名; 触发控制单元，其将解码的指令存储在匹配存储器中等待，并且选择一个即用指令并触发所选择的指令; 执行单元，其执行由点火指令指定的操作，并且在数据驱动指令的情况下，将操作结果传送到指令获取单元，或者在控制驱动指令的情况下，将操作结果转发到点火控制单元; 以及将操作结果写入寄存器的写回单元。

2. 发明授权

US08667120B2 Load control device and method thereof for controlling requests sent to a server 有权
标题翻译：负载控制装置及其方法，用于控制发送到服务器的请求
公开(公告)号：US08667120B2
公开(公告)日：2014-03-04
申请号：US12298574
申请日：2007-04-25
申请人： Ryosuke Kurebayashi , Osamu Ishida , Satoru Ota , Tsunemasa Hayashi , Kazuaki Obana
发明人： Ryosuke Kurebayashi , Osamu Ishida , Satoru Ota , Tsunemasa Hayashi , Kazuaki Obana
IPC分类号： G06F15/16 , G06F15/173 , G06F15/177 , H04L12/56 , H04L12/24 , H04L12/26
CPC分类号： H04L41/0896 , G06F9/4843 , H04L43/0894 , H04L43/16 , H04L47/10 , H04L47/193 , H04L47/27 , H04L47/39 , H04L67/32 , H04L69/16 , H04L69/165
摘要： The number of response-waiting requests which are already sent to a server (4) but to which a response is not yet returned from the server (4) is limited. To limit this number, received requests are temporarily accumulated in a buffer if the number of response-waiting requests has reached a threshold and, until the number of response-waiting requests falls below the threshold, requests are not sent from the buffer. The execution status of the server (4) is monitored, and the threshold is increased when the response time from the server (4) to a request is within an allowable range, and the threshold is decreased when the response time exceeds the allowable range. In addition, TCP connections between a load control device (3) and clients (1-1, . . . , 1-n) are aggregated so that the number of simultaneous connections of TCP connections between the server (4) and the load control device (3) becomes equal to or smaller than the threshold of the number of response-waiting requests.
摘要翻译：已经发送到服务器（4）但尚未从服务器（4）返回的响应的响应等待请求的数量受到限制。为了限制该数量，如果响应等待请求的数量已达到阈值，则接收的请求被临时累积在缓冲器中，并且直到响应等待请求的数量低于阈值，则不从缓冲器发送请求。监视服务器（4）的执行状态，并且当从服务器（4）到请求的响应时间在允许范围内时阈值增加，并且当响应时间超过允许范围时阈值减小。另外，负载控制设备（3）和客户机（1-1 ...，1-n）之间的TCP连接被聚合，使得在服务器（4）和负载控制器之间的TCP连接的同时连接的数量设备（3）变得等于或小于响应等待请求的数量的阈值。

3. 发明申请

US20090077233A1 Load Control Device and Method Thereof 有权
标题翻译：负载控制装置及其方法
公开(公告)号：US20090077233A1
公开(公告)日：2009-03-19
申请号：US12298574
申请日：2007-04-25
申请人： Ryosuke Kurebayashi , Osamu Ishida , Satoru Ota , Tsunemasa Hayashi , Kazuaki Obana
发明人： Ryosuke Kurebayashi , Osamu Ishida , Satoru Ota , Tsunemasa Hayashi , Kazuaki Obana
IPC分类号： G06F15/173
CPC分类号： H04L41/0896 , G06F9/4843 , H04L43/0894 , H04L43/16 , H04L47/10 , H04L47/193 , H04L47/27 , H04L47/39 , H04L67/32 , H04L69/16 , H04L69/165
摘要： The number of response-waiting requests which are already sent to a server (4) but to which a response is not yet returned from the server (4) is limited. To limit this number, received requests are temporarily accumulated in a buffer if the number of response-waiting requests has reached a threshold and, until the number of response-waiting requests falls below the threshold, requests are not sent from the buffer. The execution status of the server (4) is monitored, and the threshold is increased when the response time from the server (4) to a request is within an allowable range, and the threshold is decreased when the response time exceeds the allowable range. In addition, TCP connections between a load control device (3) and clients (1-1, 1-n) are aggregated so that the number of simultaneous connections of TCP connections between the server (4) and the load control device (3) becomes equal to or smaller than the threshold of the number of response-waiting requests.
摘要翻译：已经发送到服务器（4）但尚未从服务器（4）返回的响应的响应等待请求的数量受到限制。为了限制该数量，如果响应等待请求的数量已达到阈值，则接收的请求被临时累积在缓冲器中，并且直到响应等待请求的数量低于阈值，则不从缓冲器发送请求。监视服务器（4）的执行状态，并且当从服务器（4）到请求的响应时间在允许范围内时阈值增加，并且当响应时间超过允许范围时阈值减小。此外，负载控制设备（3）和客户机（1-1,1-n）之间的TCP连接被聚合，使得服务器（4）和负载控制设备（3）之间的TCP连接的同时连接的数量变得等于或小于响应等待请求数的阈值。

4. 发明申请

US20050076188A1 Data processor 有权
标题翻译：数据处理器
公开(公告)号：US20050076188A1
公开(公告)日：2005-04-07
申请号：US10952913
申请日：2004-09-30
申请人： Hiroaki Nishikawa , Hiroshi Tomiyasu , Ryosuke Kurebayashi , Shinya Ito , Shouhei Namoto
发明人： Hiroaki Nishikawa , Hiroshi Tomiyasu , Ryosuke Kurebayashi , Shinya Ito , Shouhei Namoto
IPC分类号： G06F9/38 , G06F15/00 , G06F15/82
CPC分类号： G06F9/3836 , G06F9/3838 , G06F9/384 , G06F9/3857
摘要： A data processor capable of executing sequential processing efficiently while retaining the advantages of a prior art data-driven processor. The data processor includes: an instruction fetch unit which fetches a data-driven instruction or a control-driven instruction from an instruction memory based on an input packet or a program counter; an instruction decode unit which decodes the issued instruction and, in the case of the control-driven instruction, thereafter accesses a register and performs register renaming if a data hazard is detected; a firing control unit which stores the decoded instruction in a matching memory to wait therein, and which selects one of the ready-to-fire instructions and fires the selected instruction; an execution unit which performs an operation specified by the fired instruction and, in the case of the data-driven instruction, transfers an operation result to the instruction fetch unit, or in the case of the control-driven instruction, forwards the operation result to the firing control unit; and a write back unit which writes the operation result to a register.
摘要翻译：能够有效执行顺序处理的数据处理器，同时保持现有技术的数据驱动处理器的优点。数据处理器包括：指令提取单元，其基于输入分组或程序计数器从指令存储器取出数据驱动指令或控制驱动指令; 指令解码单元，其对所发出的指令进行解码，并且在控制驱动指令的情况下，如果检测到数据危险，则访问寄存器并执行寄存器重命名; 触发控制单元，其将解码的指令存储在匹配存储器中等待，并且选择一个即用指令并触发所选择的指令; 执行单元，其执行由点火指令指定的操作，并且在数据驱动指令的情况下，将操作结果传送到指令获取单元，或者在控制驱动指令的情况下，将操作结果转发到点火控制单元; 以及将操作结果写入寄存器的写回单元。

5. 发明授权

US06813703B2 Emulation system for data-driven processor 失效
标题翻译：数据驱动处理器的仿真系统
公开(公告)号：US06813703B2
公开(公告)日：2004-11-02
申请号：US10350127
申请日：2003-01-24
申请人： Hiroaki Nishikawa , Yasuhiro Wabiko , Ryosuke Kurebayashi , Shinya Ito
发明人： Hiroaki Nishikawa , Yasuhiro Wabiko , Ryosuke Kurebayashi , Shinya Ito
IPC分类号： G06F9455
CPC分类号： G06F9/455 , G06F9/4494
摘要： An emulation system for data-driven processors aims at shortening the emulation time by employing parallel processing techniques without increasing overhead. The emulation system emulates virtual data-driven processors by using real data-driven processors. The emulation is performed by dividing the functionality of the processor into a data path and a timing path. In the data path emulation, each virtual packet to be processed in the virtual processor is expressed as a PACKET message, and the processing operation of the virtual packet is evaluated for each functional block. In the timing path emulation, a SEND signal and an ACK signal, to be controlled by a self-timed transfer control mechanism and a gate logic, are expressed as a SEND message and an ACK message, respectively, and stage-to-stage transfer operations of the SEND signal and the ACK signal are evaluated.
摘要翻译：用于数据驱动处理器的仿真系统旨在通过采用并行处理技术来缩短仿真时间，而不会增加开销。仿真系统通过使用真正的数据驱动处理器来模拟虚拟数据驱动处理器。通过将处理器的功能划分为数据路径和定时路径来执行仿真。在数据路径仿真中，在虚拟处理器中要处理的每个虚拟分组被表示为PACKET消息，并且为每个功能块评估虚拟分组的处理操作。在定时路径仿真中，要由自定时传输控制机制和门逻辑控制的SEND信号和ACK信号分别表示为SEND消息和ACK消息，并且分阶段传送评估SEND信号和ACK信号的操作。

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