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1. 发明授权

US07279937B2 Programmable amplitude line driver 失效
标题翻译：可编程幅度线驱动器
公开(公告)号：US07279937B2
公开(公告)日：2007-10-09
申请号：US11339008
申请日：2006-01-25
申请人： Mehran Aliahmad , Russ Brown , Ivan Chan , Kristopher Kshonze
发明人： Mehran Aliahmad , Russ Brown , Ivan Chan , Kristopher Kshonze
IPC分类号： H03K19/094 , H03K19/0175
CPC分类号： H04L25/0276 , G11C7/1051 , G11C7/1069 , G11C7/1078 , G11C7/1096 , H03F3/45183 , H03F3/45632 , H03F2203/45222 , H03F2203/45642 , H03F2203/45681 , H03F2203/45696 , H03F2203/45726 , H03K19/018585 , H04L25/0282
摘要： Embodiments of the invention include an integrated circuit including a line driver. The integrated circuit includes a voltage mode driver comprising complementary first and second input voltage drivers, a programmable resistor network and a current mode driver. The programmable resistor network allows the amplitude of the line driver outputs to be controlled based on the particular resistor connections in the programmable resistor network. Also, the differential impedance of the integrated circuit and the common mode impedance of the integrated circuit are based on the resistance values of the resistors in the programmable resistor network.
摘要翻译：本发明的实施例包括一种包括线路驱动器的集成电路。集成电路包括电压模式驱动器，其包括互补的第一和第二输入电压驱动器，可编程电阻器网络和电流模式驱动器。可编程电阻网络允许基于可编程电阻网络中的特定电阻器连接来控制线路驱动器输出的幅度。此外，集成电路的差分阻抗和集成电路的共模阻抗基于可编程电阻器网络中的电阻器的电阻值。

2. 发明授权

US5105055A Tunnelled multiconductor system and method 失效
标题翻译：隧道多导体系统和方法
公开(公告)号：US5105055A
公开(公告)日：1992-04-14
申请号：US598948
申请日：1990-10-17
申请人： William C. Mooney , Joseph R, Santandreu , Kristopher Kshonze
发明人： William C. Mooney , Joseph R, Santandreu , Kristopher Kshonze
IPC分类号： H01B7/08 , H01R12/62 , H01R12/77 , H05K1/00 , H05K1/02
CPC分类号： H01R12/62 , H01R12/777 , H05K1/024 , H05K1/0393
摘要： A tunnel multiconnect system comprising a substrate of flexible dielectric material, a plurality of at least three first line conductors supported on the substrate to form a multiconductor pattern, a second conductor shaped to form a ground plane, a structure for mechanically positioning the second conductor in spaced relation to the multiconductor pattern to form a tunnel therebetween, and connectors located at each end of the first conductors for coupling the first conductors and the ground plane to respective multiport terminals of electrical subassemblies thereby forming a flexible high speed ribbon interconnect system.
摘要翻译：一种隧道多连接系统，包括柔性电介质材料的衬底，多个至少三个第一线路导体，其被支撑在所述衬底上以形成多导体图案，第二导体成形为形成接地平面，用于将所述第二导体机械地定位的结构与多导体图案间隔开，以形成隧道，以及位于第一导体的每一端的连接器，用于将第一导体和接地平面耦合到电子组件的相应多端子端子，从而形成柔性高速带状互连系统。

3. 发明申请

US20070182615A1 PROGRAMMABLE AMPLITUDE LINE DRIVER 失效
标题翻译：可编程电平线驱动器
公开(公告)号：US20070182615A1
公开(公告)日：2007-08-09
申请号：US11339008
申请日：2006-01-25
申请人： Mehran Aliahmad , Russ Brown , Ivan Chan , Kristopher Kshonze
发明人： Mehran Aliahmad , Russ Brown , Ivan Chan , Kristopher Kshonze
IPC分类号： H03M1/78
CPC分类号： H04L25/0276 , G11C7/1051 , G11C7/1069 , G11C7/1078 , G11C7/1096 , H03F3/45183 , H03F3/45632 , H03F2203/45222 , H03F2203/45642 , H03F2203/45681 , H03F2203/45696 , H03F2203/45726 , H03K19/018585 , H04L25/0282
摘要： Embodiments of the invention include an integrated circuit including a line driver. The integrated circuit includes a voltage mode driver comprising complementary first and second input voltage drivers, a programmable resistor network and a current mode driver. The programmable resistor network allows the amplitude of the line driver outputs to be controlled based on the particular resistor connections in the programmable resistor network. Also, the differential impedance of the integrated circuit and the common mode impedance of the integrated circuit are based on the resistance values of the resistors in the programmable resistor network.
摘要翻译：本发明的实施例包括一种包括线路驱动器的集成电路。集成电路包括电压模式驱动器，其包括互补的第一和第二输入电压驱动器，可编程电阻器网络和电流模式驱动器。可编程电阻网络允许基于可编程电阻网络中的特定电阻器连接来控制线路驱动器输出的幅度。此外，集成电路的差分阻抗和集成电路的共模阻抗基于可编程电阻器网络中的电阻器的电阻值。

4. 发明授权

US06356218B1 Correction of DC offset in data bus structures at the receiver 失效
标题翻译：接收机数据总线结构中DC偏移的校正
公开(公告)号：US06356218B1
公开(公告)日：2002-03-12
申请号：US09568504
申请日：2000-05-11
申请人： Russell W. Brown , Kristopher Kshonze , Ivan Chan , Mehran Aliahmad
发明人： Russell W. Brown , Kristopher Kshonze , Ivan Chan , Mehran Aliahmad
IPC分类号： H03M110
CPC分类号： H03M1/1295 , H03M1/1019 , H03M1/12
摘要： DC offset introduced into a differential signal is compensated for by DC offset correction circuitry. The DC offset correction circuitry receives a known training pattern of alternating logic high and logic low levels (i.e., 10101010 etc.). In one embodiment, the received signal is integrated and the result compared to a predetermined reference level. The result of the comparison is used to adjust a DC offset correction value that is added to the received signal. This process is iteratively performed until successive results of the comparison indicate that the DC offset has been compensated for. In another embodiment, the duty-cycle of the received signal is calculated. The result of the duty-cycle calculation is used to iteratively adjust the DC offset correction value.
摘要翻译：引入到差分信号的DC偏移由DC偏移校正电路补偿。 DC偏移校正电路接收交替逻辑高电平和逻辑低电平（即10101010等）的已知训练模式。在一个实施例中，所接收的信号被积分，并且结果与预定的参考电平相比较。比较结果用于调整附加到接收信号的DC偏移校正值。迭代地执行该过程，直到比较的连续结果指示已经补偿了DC偏移。在另一个实施例中，计算接收信号的占空比。使用占空比计算的结果来迭代地调整DC偏移校正值。

5. 发明授权

US06794920B1 Sampled analog DC offset correction for data bus structures 失效
标题翻译：数据总线结构的采样模拟直流偏移校正
公开(公告)号：US06794920B1
公开(公告)日：2004-09-21
申请号：US09569036
申请日：2000-05-11
申请人： Mehran Aliahmad , Kristopher Kshonze , Russell W. Brown
发明人： Mehran Aliahmad , Kristopher Kshonze , Russell W. Brown
IPC分类号： H03K508
CPC分类号： H04L25/063 , H03K5/003 , H03K5/08
摘要： A circuit for measuring and compensating for DC offset introduced into a differential signal due to, for example, terminator mismatches and interconnect resistance, is described herein. The circuit includes a plurality of capacitors that store test values of a differential signal, a summer, a comparator, a digital counter, and an analog-to-digital converter. The summer sums signals from the plurality of capacitors and a dc offset correction signal from the analog-to-digital converter. A differential output from the summer is processed by the comparator to generate a binary output signal that is used to recursively modify the value of the dc offset correction signal until the dc offset correction signal stabilizes.
摘要翻译：本文描述了用于测量和补偿由于例如终端错误和互连电阻引入到差分信号中的DC偏移的电路。该电路包括存储差分信号，加法器，比较器，数字计数器和模数转换器的测试值的多个电容器。夏季对来自多个电容器的信号和来自模拟 - 数字转换器的直流偏移校正信号进行求和。比较器处理来自加法器的差分输出，以产生二进制输出信号，用于递归地修改直流偏移校正信号的值，直到直流偏移校正信号稳定。

6. 发明授权

US06642868B1 Apparatus and method for the correction of DC offset in data bus structures at the receiver 失效
标题翻译：用于在接收机处校正数据总线结构中的直流偏移的装置和方法
公开(公告)号：US06642868B1
公开(公告)日：2003-11-04
申请号：US10051137
申请日：2002-01-22
申请人： Russell W. Brown , Kristopher Kshonze , Ivan Chan , Mehran Aliahmad
发明人： Russell W. Brown , Kristopher Kshonze , Ivan Chan , Mehran Aliahmad
IPC分类号： H03M110
CPC分类号： H03M1/1295 , H03M1/1019 , H03M1/12
摘要： DC offset introduced into a differential signal is compensated for by DC offset correction circuitry. The DC offset correction circuitry receives a known training pattern of alternating logic high and logic low levels (i.e., 10101010 etc.). In one embodiment, the received signal is integrated and the result compared to a predetermined reference level. The result of the comparison is used to adjust a DC offset correction value that is added to the received signal. This process is iteratively performed until successive results of the comparison indicate that the DC offset has been compensated for in another embodiment, the duty-cycle of the received signal is calculated. The result of the duty-cycle calculation is used to iteratively adjust the DC offset correction value.
摘要翻译：引入到差分信号的DC偏移由DC偏移校正电路补偿。 DC偏移校正电路接收交替逻辑高电平和逻辑低电平（即10101010等）的已知训练模式。在一个实施例中，所接收的信号被积分，并且结果与预定的参考电平相比较。比较结果用于调整附加到接收信号的DC偏移校正值。迭代地执行该过程，直到比较的连续结果指示在另一个实施例中已经补偿了DC偏移，则计算接收信号的占空比。使用占空比计算的结果来迭代地调整DC偏移校正值。

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