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1. 发明授权

US08569130B2 Forming air gaps in memory arrays and memory arrays with air gaps thus formed 有权
标题翻译：在由此形成的气隙的存储器阵列和存储器阵列中形成气隙
公开(公告)号：US08569130B2
公开(公告)日：2013-10-29
申请号：US13192763
申请日：2011-07-28
申请人： James Mathew , Gordon Haller , Ronald A. Weimer , John Hopkins , Vinayak K. Shamanna , Sanjeev Sapra
发明人： James Mathew , Gordon Haller , Ronald A. Weimer , John Hopkins , Vinayak K. Shamanna , Sanjeev Sapra
IPC分类号： H01L21/336
CPC分类号： H01L29/78 , H01L21/764 , H01L27/11524 , H01L27/1157
摘要： Methods of forming air gaps in memory arrays and memory arrays with air gaps thus formed are disclosed. One such method may include forming an isolation region, having a first dielectric, through a charge-storage structure that is over a semiconductor, the isolation region extending into the semiconductor; forming a second dielectric over the isolation region and charge-storage structure; and forming an air gap in the isolation region so that the air gap passes through the charge-storage structure and so that a thickness of the first dielectric is between the air gap and the second dielectric.
摘要翻译：公开了在如此形成的具有气隙的存储器阵列和存储器阵列中形成气隙的方法。一种这样的方法可以包括通过半导体上的电荷存储结构形成具有第一电介质的隔离区域，所述隔离区域延伸到半导体中; 在隔离区域和电荷存储结构上形成第二电介质; 并且在隔离区域中形成气隙，使得气隙通过电荷存储结构，并且第一电介质的厚度在气隙和第二电介质之间。

2. 发明申请

US20110147826A1 Methods Of Forming Memory Cells 有权
标题翻译：形成记忆细胞的方法
公开(公告)号：US20110147826A1
公开(公告)日：2011-06-23
申请号：US13039600
申请日：2011-03-03
申请人： Ronald A. Weimer
发明人： Ronald A. Weimer
IPC分类号： H01L29/792 , H01L21/336
CPC分类号： H01L21/28273 , H01L21/28282 , H01L27/115 , H01L27/11521 , H01L27/11524 , H01L27/11568
摘要： Some embodiments include methods of utilizing polysilazane in forming non-volatile memory cells. The memory cells may be multi-level cells (MLCs). The polysilazane may be converted to silicon nitride, silicon dioxide, or silicon oxynitride with thermal processing and exposure to an ambient that contains one or both of oxygen and nitrogen. The methods may include using the polysilazane in forming a charge trapping layer of a non-volatile memory cell. The methods may alternatively, or additionally include using the polysilazane in forming intergate dielectric material of a non-volatile memory cell. Some embodiments include methods of forming memory cells of a NAND memory array.
摘要翻译：一些实施方案包括在形成非挥发性记忆体中使用聚硅氮烷的方法。存储器单元可以是多级单元（MLC）。聚硅氮烷可以通过热加工转化为氮化硅，二氧化硅或氮氧化硅，并暴露于含有氧和氮的一种或两种的环境中。所述方法可以包括使用聚硅氮烷形成非易失性存储单元的电荷捕获层。所述方法可以或另外包括使用聚硅氮烷形成非易失性存储单元的隔间介电材料。一些实施例包括形成NAND存储器阵列的存储单元的方法。

3. 发明申请

US20100282164A1 METHODS AND SYSTEMS FOR CONTROLLING TEMPERATURE DURING MICROFEATURE WORKPIECE PROCESSING, E.G., CVD DEPOSITION 有权
标题翻译：微生物加工过程中控制温度的方法和系统，E.G.，CVD沉积
公开(公告)号：US20100282164A1
公开(公告)日：2010-11-11
申请号：US12840153
申请日：2010-07-20
申请人： Kevin L. Beaman , Trung T. Doan , Lyle D. Breiner , Ronald A. Weimer , Er-Xuan Ping , David J. Kubista , Cem Basceri , Lingyi A. Zheng
发明人： Kevin L. Beaman , Trung T. Doan , Lyle D. Breiner , Ronald A. Weimer , Er-Xuan Ping , David J. Kubista , Cem Basceri , Lingyi A. Zheng
IPC分类号： C23C16/00 , B05C11/00
CPC分类号： C23C16/00 , C23C16/46
摘要： The present disclosure provides methods and systems for controlling temperature. The method has particular utility in connection with controlling temperature in a deposition process, e.g., in depositing a heat-reflective material via CVD. One exemplary embodiment provides a method that involves monitoring a first temperature outside the deposition chamber and a second temperature inside the deposition chamber. An internal temperature in the deposition chamber can be increased in accordance with a ramp profile by (a) comparing a control temperature to a target temperature, and (b) selectively delivering heat to the deposition chamber in response to a result of the comparison. The target temperature may be determined in accordance with the ramp profile, but the control temperature in one implementation alternates between the first temperature and the second temperature.
摘要翻译：本公开提供了用于控制温度的方法和系统。该方法在沉积工艺中控制温度，例如通过CVD沉积热反射材料方面具有特别的用途。一个示例性实施例提供了一种方法，其涉及监测沉积室外的第一温度和沉积室内的第二温度。通过（a）将控制温度与目标温度进行比较，可以根据斜坡分布来增加沉积室中的内部温度，以及（b）响应于比较的结果，选择性地将热量输送到沉积室。目标温度可以根据斜坡分布来确定，但是一个实现中的控制温度在第一温度和第二温度之间交替。

4. 发明授权

US07576398B2 Method of composite gate formation 有权
标题翻译：复合栅极形成方法
公开(公告)号：US07576398B2
公开(公告)日：2009-08-18
申请号：US11513658
申请日：2006-08-31
申请人： Ronald A Weimer
发明人： Ronald A Weimer
IPC分类号： H01L29/76
CPC分类号： H01L21/28185 , H01L21/28061 , H01L21/28194 , H01L21/28202 , H01L21/28229 , H01L29/511 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/78
摘要： Methods for forming a nitride barrier film layer in semiconductor devices such as gate structures, and barrier layers, semiconductor devices and gate electrodes are provided. The nitride layer is particularly useful as a barrier to boron diffusion into an oxide film. The nitride barrier layer is formed by selectively depositing silicon onto an oxide substrate as a thin layer, and then thermally annealing the silicon layer in a nitrogen-containing species or exposing the silicon to a plasma source of nitrogen to nitridize the silicon layer.
摘要翻译：提供了在诸如栅极结构和势垒层，半导体器件和栅电极的半导体器件中形成氮化物阻挡膜层的方法。氮化物层特别可用作硼扩散到氧化物膜中的阻挡层。氮化物阻挡层通过将硅选择性地沉积到氧化物衬底上作为薄层而形成，然后对含氮物质中的硅层进行热退火或者将硅暴露于等离子体氮源以使硅层氮化。

5. 发明申请

US20080245301A1 Deposition Apparatuses 审中-公开
标题翻译：沉积装置
公开(公告)号：US20080245301A1
公开(公告)日：2008-10-09
申请号：US12140438
申请日：2008-06-17
申请人： Ronald A. Weimer
发明人： Ronald A. Weimer
IPC分类号： C23C16/00
CPC分类号： C23C16/45546 , C23C16/4557 , C23C16/45578
摘要： The invention includes deposition methods and apparatuses which can be utilized during atomic layer deposition or chemical vapor deposition. A heated surface is provided between a stack of semiconductor substrates and a precursor inlet, and configured so that problematic side reactions occur proximate the heated surface rather than proximate the semiconductor substrates. The precursor inlet can be one of a plurality of precursor inlets, and the heated surface can be one of a plurality of heated surfaces.
摘要翻译：本发明包括可以在原子层沉积或化学气相沉积期间使用的沉积方法和装置。加热表面设置在半导体衬底的堆叠和前体入口之间，并且被配置为使得有问题的副反应发生在加热表面附近，而不是靠近半导体衬底。前体入口可以是多个前体入口之一，并且加热的表面可以是多个加热表面中的一个。

6. 发明授权

US07422635B2 Methods and apparatus for processing microfeature workpieces, e.g., for depositing materials on microfeature workpieces 失效
标题翻译：用于加工微型工件的方法和装置，例如用于在微型工件上沉积材料
公开(公告)号：US07422635B2
公开(公告)日：2008-09-09
申请号：US10652461
申请日：2003-08-28
申请人： Lingyi A. Zheng , Trung T. Doan , Lyle D. Breiner , Er-Xuan Ping , Kevin L. Beaman , Ronald A. Weimer , David J. Kubista , Cem Basceri
发明人： Lingyi A. Zheng , Trung T. Doan , Lyle D. Breiner , Er-Xuan Ping , Kevin L. Beaman , Ronald A. Weimer , David J. Kubista , Cem Basceri
IPC分类号： C23C16/00 , C23C16/455 , H01L21/306
CPC分类号： C23C16/45546 , C23C16/45578 , C23C16/4583
摘要： The present disclosure suggests several systems and methods for batch processing of microfeature workpieces, e.g., semiconductor wafers or the like. One exemplary implementation provides a method of depositing a reaction product on each of a batch of workpieces positioned in a process chamber in a spaced-apart relationship. A first gas may be delivered to an elongate first delivery conduit that includes a plurality of outlets spaced along a length of the conduit. A first gas flow may be directed by the outlets to flow into at least one of the process spaces between adjacent workpieces along a first vector that is transverse to the direction in which the workpieces are spaced. A second gas may be delivered to an elongate second delivery conduit that also has outlets spaced along its length. A second gas flow of the second gas may be directed by the outlets to flow into the process spaces along a second vector that is transverse to the first direction.
摘要翻译：本公开提出了用于批量处理微特征工件（例如半导体晶片等）的几种系统和方法。一个示例性实施方案提供了一种在间隔开的关系中将反应产物沉积在处理室中的一批工件的每一个上的方法。第一气体可以被输送到细长的第一输送管道，该第一输送管道包括沿管道的长度间隔开的多个出口。第一气流可以由出口引导，沿着横向于工件间隔开的方向的第一向量流入相邻工件之间的至少一个工艺空间。第二气体可以被输送到细长的第二输送管道，该第二输送管道也具有沿其长度间隔开的出口。第二气体的第二气流可以由出口引导，沿着横向于第一方向的第二向量流入处理空间。

7. 发明授权

US07416933B2 Methods of enabling polysilicon gate electrodes for high-k gate dielectrics 有权
标题翻译：使多晶硅栅极用于高k栅极电介质的方法
公开(公告)号：US07416933B2
公开(公告)日：2008-08-26
申请号：US10913281
申请日：2004-08-06
申请人： Ronald A. Weimer
发明人： Ronald A. Weimer
IPC分类号： H01L21/8238
CPC分类号： H01L21/823857 , H01L21/823842
摘要： Complementary transistors and methods of forming the complementary transistors on a semiconductor assembly are described. The transistors are formed with an optional interfacial oxide, such as SiO2 or oxy-nitride, to overlay a semiconductor substrate which will be conductively doped for PMOS and NMOS regions. Then a dielectric possessing a high dielectric constant of least seven or greater (also referred to as a high-k dielectric) is deposited on the interfacial oxide. The high-k dielectric is covered with a thin monolayer of metal oxide (i.e., aluminum oxide, Al2O3) that is removed from the NMOS regions, but remains in the PMOS regions. The resulting NMOS transistor diffusion regions contain predominately metal to silicon bonds that create predominately Fermi level pinning near the valence band while the resulting PMOS transistor diffusion regions contain metal to silicon bonds that create predominately Fermi level pinning near the conduction band.
摘要翻译：描述了在半导体组件上形成互补晶体管的互补晶体管和方法。晶体管形成有可选的界面氧化物，例如SiO 2或氧化氮化物，以覆盖将被导电掺杂用于PMOS和NMOS区域的半导体衬底。然后，在界面氧化物上沉积具有至少七个以上的高介电常数（也称为高k电介质）的电介质。高k电介质覆盖有从NMOS区域去除的金属氧化物（即，氧化铝，Al 2 O 3 O 3）的薄单层，但保留在 PMOS区域。所得到的NMOS晶体管扩散区域主要含有金属与硅键，其主要在价带附近产生费米能级钉扎，而所得的PMOS晶体管扩散区域含有金属与硅键，主要在导带附近产生费米能级钉扎。

8. 发明授权

US07407892B2 Deposition methods 有权
标题翻译：沉积方法
公开(公告)号：US07407892B2
公开(公告)日：2008-08-05
申请号：US11127945
申请日：2005-05-11
申请人： Ronald A. Weimer
发明人： Ronald A. Weimer
IPC分类号： H01L21/44 , H01L21/31
CPC分类号： C23C16/45546 , C23C16/4557 , C23C16/45578
摘要： The invention includes deposition methods and apparatuses which can be utilized during atomic layer deposition or chemical vapor deposition. A heated surface is provided between a stack of semiconductor substrates and a precursor inlet, and configured so that problematic side reactions occur proximate the heated surface rather than proximate the semiconductor substrates. The precursor inlet can be one of a plurality of precursor inlets, and the heated surface can be one of a plurality of heated surfaces.
摘要翻译：本发明包括可以在原子层沉积或化学气相沉积期间使用的沉积方法和装置。加热表面设置在半导体衬底的堆叠和前体入口之间，并且被配置为使得有问题的副反应发生在加热表面附近，而不是靠近半导体衬底。前体入口可以是多个前体入口之一，并且加热的表面可以是多个加热表面中的一个。

9. 发明授权

US07279398B2 Microfeature workpiece processing apparatus and methods for controlling deposition of materials on microfeature workpieces 有权
标题翻译：微型工件加工设备及控制材料沉积在微型工件上的方法
公开(公告)号：US07279398B2
公开(公告)日：2007-10-09
申请号：US11327794
申请日：2006-01-06
申请人： Cem Basceri , Trung T. Doan , Ronald A. Weimer , Kevin L. Beaman , Lyle D. Breiner , Lingyi A. Zheng , Er-Xuan Ping , Demetrius Sarigiannis , David J. Kubista
发明人： Cem Basceri , Trung T. Doan , Ronald A. Weimer , Kevin L. Beaman , Lyle D. Breiner , Lingyi A. Zheng , Er-Xuan Ping , Demetrius Sarigiannis , David J. Kubista
IPC分类号： H01L21/20 , H01L21/36 , H01L21/302 , H01L21/461 , H01L21/469
CPC分类号： C23C16/45527 , C23C16/34 , C23C16/45546
摘要： The present disclosure provides methods and apparatus useful in depositing materials on batches of microfeature workpieces. One implementation provides a method in which a quantity of a first precursor gas is introduced to an enclosure at a first enclosure pressure. The pressure within the enclosure is reduced to a second enclosure pressure while introducing a purge gas at a first flow rate. The second enclosure pressure may approach or be equal to a steady-state base pressure of the processing system at the first flow rate. After reducing the pressure, the purge gas flow may be increased to a second flow rate and the enclosure pressure may be increased to a third enclosure pressure. Thereafter, a flow of a second precursor gas may be introduced with a pressure within the enclosure at a fourth enclosure pressure; the third enclosure pressure is desirably within about 10 percent of the fourth enclosure pressure.
摘要翻译：本公开提供了用于在批次的微特征工件上沉积材料中有用的方法和装置。一个实施方案提供了一种方法，其中一定量的第一前体气体以第一封壳压力被引入外壳。当以第一流速引入吹扫气体时，外壳内的压力降低到第二封闭压力。第二外壳压力可接近或等于处理系统在第一流量下的稳态基础压力。在降低压力之后，吹扫气体流量可以增加到第二流量，并且外壳压力可以增加到第三外壳压力。此后，第二前体气体的流动可以在第四封闭压力下以外壳内的压力引入; 第三外壳压力理想地在第四外壳压力的约10％内。

10. 发明授权

US07264768B2 Single substrate annealing of magnetoresistive structure 失效
标题翻译：磁阻结构的单基板退火
公开(公告)号：US07264768B2
公开(公告)日：2007-09-04
申请号：US11060794
申请日：2005-02-18
申请人： Mark E. Tuttle , Ronald A. Weimer
发明人： Mark E. Tuttle , Ronald A. Weimer
IPC分类号： F24J3/00
CPC分类号： B82Y25/00 , B82Y40/00 , H01F1/0009 , H01F41/304
摘要： A device for magnetically annealing magnetoresistive elements formed on wafers includes a heated chuck and a delivery mechanism for individually placing the wafers individually on the chuck one at a time. A coil is adjacent to the chuck and generates a magnetic field after the wafer is heated to a Néel temperature of an anti-ferromagnetic layer. A control system regulates the temperature of the heated chuck, the strength of the magnetic field, and a time period during which each chuck is heated to control the annealing process. The annealed elements are incorporated in the fabrication of magnetic memory devices.
摘要翻译：用于磁性退火在晶片上形成的磁阻元件的装置包括加热的卡盘和用于将晶片单独地单独地放置在卡盘上的输送机构。线圈与卡盘相邻，并且在将晶片加热到反铁磁层的Néel温度之后产生磁场。控制系统调节加热卡盘的温度，磁场的强度以及加热每个卡盘以控制退火过程的时间段。退火元件被结合在磁存储器件的制造中。

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