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1. 发明申请

US20090271671A1 APPARATUS AND METHOD FOR IMPROVED TEST CONTROLLABILITY AND OBSERVABILITY OF RANDOM RESISTANT LOGIC 有权
标题翻译：用于改进随机阻抗逻辑的测试可控性和可观察性的装置和方法
公开(公告)号：US20090271671A1
公开(公告)日：2009-10-29
申请号：US12110731
申请日：2008-04-28
申请人： Mary P. Kusko , Haoxing Ren , Ronald G. Walther , Rona Yaari
发明人： Mary P. Kusko , Haoxing Ren , Ronald G. Walther , Rona Yaari
IPC分类号： G01R31/3177 , G06F11/25
CPC分类号： G01R31/31707 , G01R31/318321
摘要： A method for implementing improved observability of random resistant logic included in an integrated circuit (IC) design includes configuring a multiplexer device to pass, to a preexisting storage latch within the design, one of: a signal from one or more observation points within the random resistant logic and an output of first preexisting combinational logic; and selecting a preexisting net within the IC design to generate a randomized logic signal that, in a test mode, is passed to the multiplexer device to serve as a control signal thereto; wherein, in the test mode, the existing storage latch captures data randomly selected from either the existing combinational logic and the one or more observation points and in a normal mode, the existing storage latch captures data from only the existing combinational logic, facilitating random testing of the random resistant logic in a manner that avoids adding latches to the design.
摘要翻译：一种用于实现集成电路（IC）设计中包括的随机电阻逻辑的改进的可观察性的方法包括：配置多路复用器装置，将设计中的先前存在的锁存器传递到：随机的来自一个或多个观察点的信号电阻逻辑和第一预先组合逻辑的输出; 以及选择所述IC设计中的预先存在的网络，以产生随机逻辑信号，所述随机逻辑信号在测试模式中被传递到所述多路复用器设备以用作其控制信号; 其中，在测试模式中，现有存储锁存器捕获从现有的组合逻辑和一个或多个观测点中随机选择的数据，并且在正常模式下，现有的存储锁存器仅从现有的组合逻辑中捕获数据，便于随机测试的方式，以避免向设计添加锁存器。

2. 发明授权

US07882454B2 Apparatus and method for improved test controllability and observability of random resistant logic 有权
标题翻译：用于提高随机电阻逻辑的测试可控性和可观察性的装置和方法
公开(公告)号：US07882454B2
公开(公告)日：2011-02-01
申请号：US12110731
申请日：2008-04-28
申请人： Mary P Kusko , Haoxing Ren , Ronald G Walther , Rona Yaari
发明人： Mary P Kusko , Haoxing Ren , Ronald G Walther , Rona Yaari
IPC分类号： G06F17/50
CPC分类号： G01R31/31707 , G01R31/318321
摘要： A method for implementing improved observability of random resistant logic included in an integrated circuit (IC) design includes configuring a multiplexer device to pass, to a preexisting storage latch within the design, one of: a signal from one or more observation points within the random resistant logic and an output of first preexisting combinational logic; and selecting a preexisting net within the IC design to generate a randomized logic signal that, in a test mode, is passed to the multiplexer device to serve as a control signal thereto; wherein, in the test mode, the existing storage latch captures data randomly selected from either the existing combinational logic and the one or more observation points and in a normal mode, the existing storage latch captures data from only the existing combinational logic, facilitating random testing of the random resistant logic in a manner that avoids adding latches to the design.
摘要翻译：一种用于实现集成电路（IC）设计中包括的随机电阻逻辑的改进的可观察性的方法包括：配置多路复用器装置，将设计中的先前存在的锁存器传递到：随机的来自一个或多个观察点的信号电阻逻辑和第一预先组合逻辑的输出; 以及选择所述IC设计中的预先存在的网络，以产生随机逻辑信号，所述随机逻辑信号在测试模式中被传递到所述多路复用器设备以用作其控制信号; 其中，在测试模式中，现有存储锁存器捕获从现有的组合逻辑和一个或多个观测点中随机选择的数据，并且在正常模式下，现有的存储锁存器仅从现有的组合逻辑中捕获数据，便于随机测试的方式，以避免向设计添加锁存器。

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