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    • 8. 发明授权
    • Electrical filter circuit utilizing charge transfer delay lines
utilizing individual charge transfer delay elements
    • 利用各种电荷转移延迟元件的电荷转移延迟线的电滤波器电路
    • US4281297A
    • 1981-07-28
    • US60195
    • 1979-07-24
    • Hermann BetzlErnst HebenstreitRoland Schreiber
    • Hermann BetzlErnst HebenstreitRoland Schreiber
    • H03H15/02H03H17/02G11C27/00
    • H03H15/02
    • A filter circuit utilizing charge transfer delay lines having individual CTD elements utilizing four-terminal resonators each of which is designated as a self-contained closed looped circuit and which determine the frequency dependent transmission characteristics of the filter circuit and wherein successive four-terminal resonators are interconnected by way of a coupling circuit. The invention utilizes the coupling circuit mounted between adjacent four-terminal resonators which are constructed simply as possible and utilizing integrated circuit techniques. Amplifiers are connected in parallel with the input and/or the output of the individual four-terminal resonators and the signal flow direction of the amplifiers corresponds to that of parallel connected CTD lines and the series lines of the coupling circuit and the amplifiers have unidirectional transmission characteristics and an inverting amplifier is contained in at least one of the series lines.
    • 利用具有各自的CTD元件的电荷转移延迟线的滤波器电路,其使用四端谐振器,每个CTD元件被指定为独立闭环电路,并且确定滤波电路的频率相关传输特性,并且其中连续的四端谐振器是 通过耦合电路互连。 本发明利用安装在相邻的四端谐振器之间的耦合电路,它们被简单地构成并且利用集成电路技术。 放大器与单个四端谐振器的输入和/或输出并联连接,放大器的信号流动方向对应于并联CTD线的信号流动方向,并且耦合电路和放大器的串联线具有单向传输 特性和反相放大器包含在串联线中的至少一个中。
    • 9. 发明授权
    • Resonator formed in integrated MOS technology utilizing switched
capacitors
    • 谐振器采用集成MOS技术,采用开关电容器
    • US4266205A
    • 1981-05-05
    • US51701
    • 1979-06-25
    • Hermann BetzlErnst HebenstreitRoland Schreiber
    • Hermann BetzlErnst HebenstreitRoland Schreiber
    • G06G7/161G06G7/16G06G7/22H03H15/02H03H17/00H03H19/00H03H17/06H03H17/04
    • H03H17/00G06G7/16G06G7/22H03H15/02H03H19/004
    • A resonator circuit formed in MOS technology for scanned analog signals, wherein such circuits are constructed for use with accumulators and information processing is accomplished by means of switched capacitors which are charged or respectively connected to each other by way of clock pulse transistors. In the present invention, the realization of general ladder networks or branching circuits for builders in single layer MOS techniques is accomplished by utilizing a second continuous branch which is switched to a first accumulator stage by clock pulse switches and is connected with a reference potential through a capacitor as well as to a further accumulator input through a series switch. The signal series arms are connected with the outputs of the total accumulator arrangement by way of time delay transit elements. The total accumulator arrangement is expanded to a resonator of the type of a four pole network having two inputs to which one respective transmission and one respective reflection output is assigned by utilizing difference elements and transfer elements. The arrangement of the invention is suitable for use as general branching filter circuits, and an increase of the dynamic range by better suppression of the clock pulse pickup and the harmonic distortion of the second order occurs by utilizing push-pull arrangements.
    • 一种用于扫描模拟信号的MOS技术中形成的谐振器电路,其中这种电路被构造为与累加器一起使用并且信息处理是借助于通过时钟脉冲晶体管彼此充电或分别连接的开关电容来实现的。 在本发明中,通过利用通过时钟脉冲开关切换到第一累加器级的第二连续分支来实现单层MOS技术中用于构建器的通用梯形网络或分支电路的实现,并且通过一个参考电位 电容器以及通过串联开关的另一个蓄电池输入。 信号序列臂通过时间延迟传递元件与总累加器布置的输出连接。 总累加器布置扩展到具有两个输入的四极网络类型的谐振器,通过利用差分元件和传递元件,一个相应的透射和一个相应的反射输出被分配到该输入。 本发明的装置适合用作普通分波器滤波电路,通过利用推挽装置,可以更好地抑制时钟脉冲拾取和二阶谐波失真,从而提高动态范围。