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1. 发明授权

US07388932B1 Fully parallel multi-channel demodulator 有权
标题翻译：全并行多通道解调器
公开(公告)号：US07388932B1
公开(公告)日：2008-06-17
申请号：US10335209
申请日：2002-12-30
申请人： WeiMin Zhang , Vladimir Radionov , Roger Stenerson , Bin-Fan Liu , Yu Kou
发明人： WeiMin Zhang , Vladimir Radionov , Roger Stenerson , Bin-Fan Liu , Yu Kou
IPC分类号： H03K9/00
CPC分类号： H04L27/0012 , H04L1/004 , H04L7/0079 , H04L25/03006
摘要： An improved multi-channel demodulator is provided. The improved demodulator includes an automatic gain control, a data buffer and a demodulation engine. Data from various RF channels are processed by the automatic gain control in order to keep the data at their respective constant levels. Output from the automatic gain control is passed to the data buffer for storage. Corresponding data from a selected channel is then processed by the demodulation engine. The improved demodulator is able to operate in any one of three operating modes, namely, a data processing mode, a channel switching mode and a waiting mode. In the data processing mode, the demodulation engine processes the channel data that is currently loaded into the demodulation engine. In the channel switching mode, the demodulation engine stores the current channel data into the data buffer and retrieves and loads channel data from another channel for processing. In addition, status and history information relating to the current channel data is stored into a channel status memory and status and history information relating to the next channel to be processed is retrieved from the channel status memory. In one exemplary aspect, in order to reduce the channel switching time, status and history information relating to the next channel to be processed is preloaded during the previous data processing mode. In the waiting mode, the demodulation engine awaits further processing instructions to decide whether to enter into either the data processing mode or the channel switching mode.
摘要翻译：提供改进的多通道解调器。改进的解调器包括自动增益控制，数据缓冲器和解调引擎。来自各种RF信道的数据由自动增益控制处理，以便将数据保持在它们各自的恒定水平。自动增益控制的输出传递到数据缓冲区进行存储。然后由解调引擎处理来自选定信道的对应数据。改进的解调器能够以三种操作模式中的任一种操作，即数据处理模式，信道切换模式和等待模式。在数据处理模式中，解调引擎处理当前加载到解调引擎中的信道数据。在信道切换模式中，解调引擎将当前信道数据存储到数据缓冲器中，并从另一个信道检索和加载信道数据进行处理。此外，与当前频道数据相关的状态和历史信息被存储到频道状态存储器中，并且从频道状态存储器检索与要处理的下一频道有关的状态和历史信息。在一个示例性方面，为了减少频道切换时间，在先前的数据处理模式期间预先加载与要处理的下一频道相关的状态和历史信息。在等待模式中，解调引擎等待进一步的处理指令来决定是进入数据处理模式还是进入信道切换模式。

2. 发明授权

US07200189B1 Method and system for providing adaptive timing recovery for low power application 有权
标题翻译：为低功率应用提供自适应定时恢复的方法和系统
公开(公告)号：US07200189B1
公开(公告)日：2007-04-03
申请号：US10269795
申请日：2002-10-11
申请人： Roger Stenerson , WeiMin Zhang
发明人： Roger Stenerson , WeiMin Zhang
IPC分类号： H03D3/18 , H03D3/24
CPC分类号： H04L7/0029
摘要： A system for providing adaptive timing recovery is provided. In an exemplary embodiment, the system includes a fractional resampler, an error function module and a loop filter, arranged collectively to form a timing recovery loop. In an initial mode, the error function module compares the output of the fractional resampler with a reference signal to determine an error, if any. An error signal is generated accordingly based on the error. The error signal is then provided to the loop filter allowing the loop filter to generate a correction signal. The correction signal is provided to the fractional resampler to allow the fractional resampler to generate an output which minimizes the error. When the error function module determines that the error is within an acceptable range, i.e., a timing lock is achieved, the system goes into a steady mode. In the steady mode, the error function module is directed to execute at a slower rate. By executing at a slower rate, the error function module is able to operate at a reduced level of power consumption.
摘要翻译：提供了一种用于提供自适应定时恢复的系统。在示例性实施例中，系统包括集中布置以形成定时恢复环路的分数重采样器，误差功能模块和环路滤波器。在初始模式下，误差功能模块将分数重采样器的输出与参考信号进行比较，以确定是否存在错误。基于该错误相应地生成错误信号。然后将误差信号提供给环路滤波器，使得环路滤波器产生校正信号。校正信号被提供给分数重采样器，以允许分数重采样器产生最小化误差的输出。当错误功能模块确定错误在可接受的范围内时，即实现定时锁定时，系统进入稳定模式。在稳定模式下，错误功能模块被指示以较慢的速率执行。通过以较慢的速率执行，误差功能模块能够以降低的功耗水平进行操作。

3. 发明授权

US07289424B1 Method and system for implementing a baseband compression scheme for a nonlinear multiplying up-converter for QPSK and OQPSK 有权
标题翻译：用于实现用于QPSK和OQPSK的非线性乘法上变频器的基带压缩方案的方法和系统
公开(公告)号：US07289424B1
公开(公告)日：2007-10-30
申请号：US10269741
申请日：2002-10-11
申请人： Roger Stenerson , WeiMin Zhang
发明人： Roger Stenerson , WeiMin Zhang
IPC分类号： H04J9/00
CPC分类号： H04L27/2092 , H04L27/20
摘要： A system for implementing a base band compression scheme for a nonlinear multiplying up-converter for QPSK and OQPSK includes a bit combining module, a quadrant remap module, a look-up table (LUT) and a zoom adjust module. The bit combining module is configured to generate an address based on a number of symbols received as input data. Using the address provided by the bit combining module, the quadrant remap module remaps symbols from quadrants “2”, “3” and “4” to quadrant “1” and generates signals to look up corresponding output data from the LUT. The zoom adjust module generates a number of solutions corresponding to the input data using the corresponding output data retrieved from the LUT. The zoom adjust module is then used to select the best output from the solutions to provide a smooth output signal that does not have any discontinuities.
摘要翻译：用于实现用于QPSK和OQPSK的非线性乘法上变频器的基带压缩方案的系统包括位组合模块，象限重映射模块，查找表（LUT）和变焦调整模块。位组合模块被配置为基于作为输入数据接收的符号的数量来生成地址。使用比特组合模块提供的地址，象限重映射模块将象限“2”，“3”和“4”的符号重新映射到象限“1”，并生成信号以从LUT中查找相应的输出数据。变焦调整模块使用从LUT检索的相应输出数据生成与输入数据相对应的多个解。然后，缩放调整模块用于从解决方案中选择最佳输出，以提供没有任何不连续性的平滑输出信号。

4. 发明授权

US06781473B1 High-speed low-power implementation for multi-channel numerically controlled oscillator (NCO) 失效
标题翻译：用于多通道数控振荡器（NCO）的高速低功耗实现
公开(公告)号：US06781473B1
公开(公告)日：2004-08-24
申请号：US10242947
申请日：2002-09-13
申请人： John S Chiu , Roger Stenerson , Sricharan Kasetti , WeiMin Zhang
发明人： John S Chiu , Roger Stenerson , Sricharan Kasetti , WeiMin Zhang
IPC分类号： H03B2100
CPC分类号： G06F1/0353 , G06F1/0342
摘要： Method and apparatus for generating sinusoidal signals in quadrature. A numerically controlled oscillator includes a phase accumulator configured to generate a periodic multi-bit signal at a given frequency; a first memory configured to store an octant of a sinusoidal waveform; a second memory configured to store a complementary octant of the sinusoidal waveform; and a control circuit, responsive to at least a portion of the phase accumulator signal and coupled to the first and second memories, the control circuit configured to access the first and second memories in parallel and construct respective sine and cosine waves at the given frequency.
摘要翻译：用于产生正交正弦信号的方法和装置。数控振荡器包括相位累加器，其被配置为以给定频率产生周期性多位信号; 配置为存储正弦波形的八分圆的第一存储器; 第二存储器，被配置为存储所述正弦波形的互补八分圆; 以及控制电路，响应于所述相位累加器信号的至少一部分并且耦合到所述第一和第二存储器，所述控制电路被配置为并行访问所述第一和第二存储器并且以给定频率构造相应的正弦和余弦波。

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