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1. 发明申请

US20140201477A1 METHODS AND APPARATUS TO MANAGE WORKLOAD MEMORY ALLOCATION 有权
标题翻译：管理工作记忆分配的方法和设备
公开(公告)号：US20140201477A1
公开(公告)日：2014-07-17
申请号：US13992976
申请日：2011-12-27
申请人： Michael R. Greenfield , Roger Golliver
发明人： Michael R. Greenfield , Roger Golliver
IPC分类号： G06F12/02
CPC分类号： G06F3/0608 , G06F3/0604 , G06F3/0611 , G06F3/0631 , G06F3/0638 , G06F3/0647 , G06F3/0653 , G06F3/067 , G06F3/0683 , G06F9/5016 , G06F12/02 , G06F12/023 , G06F13/18 , G06F2209/501 , G06F2209/5021 , G06F2212/1044
摘要： Methods, articles of manufacture, and apparatus are disclosed to manage workload memory allocation. An example method includes identifying a primary memory and a secondary memory associated with a platform, the secondary memory having first performance metrics different from second performance metrics of the primary memory, identifying access metrics associated with a plurality of data elements invoked by a workload during execution on the platform, prioritizing a list of the plurality of data elements based on the access metrics associated with corresponding ones of the plurality of data elements, and reallocating a first one of the plurality of data elements from the primary memory to the secondary memory based on the priority of the first one of the plurality of memory elements.
摘要翻译：公开了方法，制品和装置来管理工作负载内存分配。示例性方法包括识别与平台相关联的主存储器和次存储器，辅存储器具有与主存储器的第二性能度量不同的第一性能度量，识别与执行期间由工作负载调用的多个数据元素相关联的访问度量在平台上，基于与多个数据元素中的相应数据元素相关联的访问度量优先化多个数据元素的列表，并且基于多个数据元素中的第一个数据元素从主存储器重新分配到辅助存储器多个存储元件中的第一个的优先级。

2. 发明授权

US06370639B1 Processor architecture having two or more floating-point status fields 有权
标题翻译：具有两个或多个浮点状态字段的处理器架构
公开(公告)号：US06370639B1
公开(公告)日：2002-04-09
申请号：US09169482
申请日：1998-10-10
申请人： Jerome C. Huck , Peter Markstein , Glenn T. Colon-Bonet , Alan H. Karp , Roger Golliver , Michael Morrison , Gautam B. Doshi , Guillermo Juan Rozas
发明人： Jerome C. Huck , Peter Markstein , Glenn T. Colon-Bonet , Alan H. Karp , Roger Golliver , Michael Morrison , Gautam B. Doshi , Guillermo Juan Rozas
IPC分类号： G06F9312
CPC分类号： G06F9/3865 , G06F9/30014 , G06F9/30094 , G06F9/3842
摘要： A floating-point unit of a computer includes a floating-point computation unit, floating-point registers and a floating-point status register. The floating-point status register may include a main status field and one or more alternate status fields. Each of the status fields contains flag and control information. Different floating-point operations may be associated with different status fields. Subfields of the floating-point status register may be updated dynamically during operation. The control bits of the alternate status fields may include a trap disable bit for deferring interruptions during speculative execution. A widest range exponent control bit in the status fields may be used to prevent interruptions when the exponent of an intermediate result is within the range of the register format but exceeds the range of the memory format. The floating-point data may be stored in big endian or little endian format.
摘要翻译：计算机的浮点单元包括浮点计算单元，浮点寄存器和浮点状态寄存器。浮点状态寄存器可以包括主状态字段和一个或多个备用状态字段。每个状态字段都包含标志和控制信息。不同的浮点运算可能与不同的状态字段相关联。浮点状态寄存器的子字段可以在操作期间动态更新。替代状态字段的控制位可以包括用于在推测执行期间推迟中断的陷阱禁止位。当中间结果的指数在寄存器格式的范围内但超出存储器格式的范围时，可以使用状态字段中的最大范围指数控制位来防止中断。浮点数据可以以大端或小端格式存储。

3. 发明授权

US09141386B2 Vector logical reduction operation implemented using swizzling on a semiconductor chip 有权
标题翻译：使用在半导体芯片上进行旋转实现的矢量逻辑减少操作
公开(公告)号：US09141386B2
公开(公告)日：2015-09-22
申请号：US12890485
申请日：2010-09-24
申请人： Jeff Wiedemeier , Sridhar Samudrala , Roger Golliver
发明人： Jeff Wiedemeier , Sridhar Samudrala , Roger Golliver
IPC分类号： G06F9/305 , G06F9/30 , G06F15/76 , G06F9/06 , G06F7/00
CPC分类号： G06F9/30029 , G06F7/00 , G06F9/06 , G06F9/30032 , G06F9/30036 , G06F15/76
摘要： A semiconductor processor is described. The semiconductor processor includes logic circuitry to perform a logical reduction instruction. The logic circuitry has swizzle circuitry to swizzle a vector's elements so as to form a swizzle vector. The logic circuitry also has vector logic circuitry to perform a vector logic operation on said vector and said swizzle vector.
摘要翻译：描述半导体处理器。半导体处理器包括执行逻辑减少指令的逻辑电路。逻辑电路具有旋转矢量元件的旋转电路，以便形成旋转矢量。逻辑电路还具有矢量逻辑电路，用于对所述矢量和所述旋转矢量执行矢量逻辑运算。

4. 发明申请

US20140052943A1 PROVIDING EXTENDED MEMORY SEMANTICS WITH ATOMIC MEMORY OPERATIONS 有权
标题翻译：用原子内存操作提供扩展的存储器语句
公开(公告)号：US20140052943A1
公开(公告)日：2014-02-20
申请号：US13997534
申请日：2011-12-30
申请人： Roger Golliver
发明人： Roger Golliver
IPC分类号： G06F12/00
CPC分类号： G06F9/526 , G06F8/458
摘要： A computer-implemented method and a corresponding computer system for emulation of Extended Memory Semantics (EMS) operations. The method and system include obtaining a set of computer instructions that include an EMS operation, converting the EMS operation into a corresponding atomic memory operation (AMO), and executing the AMO on at least one processor of a computer.
摘要翻译：一种用于仿真扩展内存语义（EMS）操作的计算机实现的方法和相应的计算机系统。该方法和系统包括获得一组包括EMS操作的计算机指令，将EMS操作转换为对应的原子存储器操作（AMO），以及在计算机的至少一个处理器上执行AMO。

5. 发明授权

US09092213B2 Functional unit for vector leading zeroes, vector trailing zeroes, vector operand 1s count and vector parity calculation 有权
标题翻译：向量前导零的功能单位，向量尾随零，向量操作数1s计数和向量奇偶校验计算
公开(公告)号：US09092213B2
公开(公告)日：2015-07-28
申请号：US12890457
申请日：2010-09-24
申请人： Jeff Wiedemeier , Sridhar Samudrala , Roger Golliver , Eric W. Mahurin
发明人： Jeff Wiedemeier , Sridhar Samudrala , Roger Golliver , Eric W. Mahurin
IPC分类号： G06F7/38 , G06F9/00 , G06F9/44 , G06F15/00 , G06F9/30
CPC分类号： G06F9/30036 , G06F9/30014 , G06F9/30018
摘要： A method of performing vector operations on a semiconductor chip is described. The method includes performing a first vector instruction with a vector functional unit implemented on the semiconductor chip and performing a second vector instruction with the vector functional unit. The first vector instruction is a vector multiply add instruction. The second vector instruction is a vector leading zeros count instruction.
摘要翻译：描述了在半导体芯片上执行向量操作的方法。该方法包括利用在半导体芯片上实现的矢量功能单元执行第一矢量指令，并用矢量功能单元执行第二矢量指令。第一个向量指令是一个向量乘法加法指令。第二个向量指令是向量前导零计数指令。

6. 发明申请

US20120079233A1 VECTOR LOGICAL REDUCTION OPERATION IMPLEMENTED ON A SEMICONDUCTOR CHIP 有权
标题翻译：在半导体芯片上执行的矢量逻辑减少操作
公开(公告)号：US20120079233A1
公开(公告)日：2012-03-29
申请号：US12890485
申请日：2010-09-24
申请人： Jeff Wiedemeier , Sridhan Samudrala , Roger Golliver
发明人： Jeff Wiedemeier , Sridhan Samudrala , Roger Golliver
IPC分类号： G06F15/76 , G06F9/06
CPC分类号： G06F9/30029 , G06F7/00 , G06F9/06 , G06F9/30032 , G06F9/30036 , G06F15/76
摘要： A semiconductor processor is described. The semiconductor processor includes logic circuitry to perform a logical reduction instruction. The logic circuitry has swizzle circuitry to swizzle a vector's elements so as to form a swizzle vector. The logic circuitry also has vector logic circuitry to perform a vector logic operation on said vector and said swizzle vector.
摘要翻译：描述半导体处理器。半导体处理器包括执行逻辑减少指令的逻辑电路。逻辑电路具有旋转矢量元件的旋转电路，以便形成旋转矢量。逻辑电路还具有矢量逻辑电路，用于对所述矢量和所述旋转矢量执行矢量逻辑运算。

7. 发明申请

US20060206943A1 Protecting software environment in isolated execution 有权
标题翻译：在孤立执行中保护软件环境
公开(公告)号：US20060206943A1
公开(公告)日：2006-09-14
申请号：US11386269
申请日：2006-03-21
申请人： Carl Ellison , Roger Golliver , Howard Herbert , Derrick Lin , Francis McKeen , Gilbert Neiger , Ken Reneris , James Sutton , Shreekant Thakkar , Millind Mittal
发明人： Carl Ellison , Roger Golliver , Howard Herbert , Derrick Lin , Francis McKeen , Gilbert Neiger , Ken Reneris , James Sutton , Shreekant Thakkar , Millind Mittal
IPC分类号： H04N7/16
CPC分类号： G06F21/53 , G06F9/468 , G06F21/562 , G06F21/57 , G06F21/74 , G06F2221/2105
摘要： A processing system has a processor that can operate in a normal ring 0 operating mode and one or more higher ring operating modes above the normal ring 0 operating mode. In addition, the processor can operate in an isolated execution mode. A memory in the processing system may include an ordinary memory area that can be accessed from the normal ring 0 operating mode, as well as an isolated memory area that can be accessed from the isolated execution mode but not from the normal ring 0 operating mode. The processing system may also include an operating system (OS) nub, as well as a key generator. The key generator may generate an OS nub key (OSNK) based at least in part on an identification of the OS nub and a master binding key (BK0) of the platform. Other embodiments are described and claimed.
摘要翻译：处理系统具有处理器，该处理器可以在正常环0操作模式和高于正常环0操作模式的一个或多个较高环操作模式下操作。此外，处理器可以在隔离的执行模式下操作。处理系统中的存储器可以包括可以从正常环0操作模式访问的普通存储器区域以及可以从隔离执行模式而不是从正常环0操作模式访问的隔离存储器区域。处理系统还可以包括操作系统（OS）nub以及密钥生成器。密钥生成器可以至少部分地基于OS nub的标识和平台的主绑定密钥（BK 0）来生成OS nub密钥（OSNK）。描述和要求保护其他实施例。

8. 发明授权

US06243734B1 Computer product and method for sparse matrices 有权
标题翻译：稀疏矩阵的计算机产品和方法
公开(公告)号：US06243734B1
公开(公告)日：2001-06-05
申请号：US09183065
申请日：1998-10-30
申请人： Gautam Doshi , Roger Golliver , Bob Norin
发明人： Gautam Doshi , Roger Golliver , Bob Norin
IPC分类号： G06F752
CPC分类号： G06F17/16
摘要： A computer program product and method for multiplying a sparse matrix by a vector are disclosed. The computer program product includes a computer readable medium for storing instructions, which, when executed by a computer, cause the computer to efficiently multiply a sparse matrix by a vector, and produce a resulting vector. The computer is made to create a first array containing the non-zero elements of the sparse matrix, and a second array containing the end_of_row position of the last non-zero element in each row of the sparse matrix. A variable is initialized, and then, for each row of the second array, the computer is made to do one of two things. Either, it equates the variable to the sum of the variable and the product of a particular element of the first array and a particular element of the vector. Or, it equates a particular element of the resulting vector to the variable, and then equates the variable to a particular value.
摘要翻译：公开了一种用于将稀疏矩阵乘以矢量的计算机程序产品和方法。计算机程序产品包括用于存储指令的计算机可读介质，指令当由计算机执行时使得计算机有效地将稀疏矩阵乘以一个向量，并产生所得到的向量。该计算机用于创建包含稀疏矩阵的非零元素的第一阵列，以及包含稀疏矩阵的每一行中最后一个非零元素的end_of_row位置的第二阵列。变量被初始化，然后，对于第二个数组的每一行，计算机被做成两件事之一。或者，它将变量等同于变量和第一个数组的特定元素与向量的特定元素的乘积之和。或者，它将所得到的向量的特定元素等同于变量，然后将变量等同于特定值。

9. 发明授权

US06212539B1 Methods and apparatus for handling and storing bi-endian words in a floating-point processor 有权
标题翻译：用于在浮点处理器中处理和存储双向字的方法和装置
公开(公告)号：US06212539B1
公开(公告)日：2001-04-03
申请号：US09169483
申请日：1998-10-10
申请人： Jerome C. Huck , Peter Markstein , Glenn T. Colon-Bonet , Alan H. Karp , Roger Golliver , Michael Morrison , Gautam B. Doshi
发明人： Jerome C. Huck , Peter Markstein , Glenn T. Colon-Bonet , Alan H. Karp , Roger Golliver , Michael Morrison , Gautam B. Doshi
IPC分类号： G06F700
CPC分类号： G06F7/768 , G06F7/483
摘要： A floating-point unit of a computer includes a floating-point computation unit, floating-point registers and a floating-point status register. The floating-point status register may include a main status field and one or more alternate status fields. Each of the status fields contains flag and control information. Different floating-point operations may be associated with different status fields. Subfields of the floating-point status register may be updated dynamically during operation. The control bits of the alternate status fields may include a trap disable bit for deferring interruptions during speculative execution. A widest range exponent control bit in the status fields may be used to prevent interruptions when the exponent of an intermediate result is within the range of the register format but exceeds the range of the memory format. The floating-point data may be stored in big endian or little endian format.
摘要翻译：计算机的浮点单元包括浮点计算单元，浮点寄存器和浮点状态寄存器。浮点状态寄存器可以包括主状态字段和一个或多个备用状态字段。每个状态字段都包含标志和控制信息。不同的浮点运算可能与不同的状态字段相关联。浮点状态寄存器的子字段可以在操作期间动态更新。替代状态字段的控制位可以包括用于在推测执行期间推迟中断的陷阱禁止位。当中间结果的指数在寄存器格式的范围内但超出存储器格式的范围时，可以使用状态字段中的最大范围指数控制位来防止中断。浮点数据可以以大端或小端格式存储。

10. 发明授权

US6151669A Methods and apparatus for efficient control of floating-point status register 有权
标题翻译：浮点状态寄存器的有效控制方法和装置
公开(公告)号：US6151669A
公开(公告)日：2000-11-21
申请号：US169481
申请日：1998-10-10
申请人： Jerome C. Huck , Peter Markstein , Glenn T. Colon-Bonet , Alan H. Karp , Roger Golliver , Michael Morrison , Gautam B. Doshi , Guillermo Juan Rozas
发明人： Jerome C. Huck , Peter Markstein , Glenn T. Colon-Bonet , Alan H. Karp , Roger Golliver , Michael Morrison , Gautam B. Doshi , Guillermo Juan Rozas
IPC分类号： G06F7/00 , G06F7/76 , G06F9/30 , G06F9/302 , G06F9/32 , G06F9/38 , G06F15/00
CPC分类号： G06F9/30014 , G06F9/30094 , G06F9/3842
摘要： A floating-point unit of a computer includes a floating-point computation it, floating-point registers and a floating-point status register. The floating-point status register may include a main status field and one or more alternate status fields. Each of the status fields contains flag and control information. Different floating-point operations may be associated with different status fields. Subfields of the floating-point status register may be updated dynamically during operation. The control bits of the alternate status fields may include a trap disable bit for deferring interruptions during speculative execution. A widest range exponent control bit in the status fields may be used to prevent interruptions when the exponent of an intermediate result is within the range of the register format but exceeds the range of the memory format. The floating-point data may be stored in big endian or little endian format.
摘要翻译：计算机的浮点单元包括浮点计算单元，浮点寄存器和浮点状态寄存器。浮点状态寄存器可以包括主状态字段和一个或多个备用状态字段。每个状态字段都包含标志和控制信息。不同的浮点运算可能与不同的状态字段相关联。浮点状态寄存器的子字段可以在操作期间动态更新。替代状态字段的控制位可以包括用于在推测执行期间推迟中断的陷阱禁止位。当中间结果的指数在寄存器格式的范围内但超出存储器格式的范围时，可以使用状态字段中的最大范围指数控制位来防止中断。浮点数据可以以大端或小端格式存储。

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