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1. 发明授权

US5659794A System architecture for improved network input/output processing 失效
标题翻译：用于改进网络输入/输出处理的系统架构
公开(公告)号：US5659794A
公开(公告)日：1997-08-19
申请号：US414900
申请日：1995-03-31
申请人： Charles R. Caldarale , Peter J. Hancock , David R. Johnson , Robert M. Malek , James R. McBreen , Hans C. Mikkelsen , Jerome J. Witalka
发明人： Charles R. Caldarale , Peter J. Hancock , David R. Johnson , Robert M. Malek , James R. McBreen , Hans C. Mikkelsen , Jerome J. Witalka
IPC分类号： H04L12/56 , H04L29/06 , H04L29/08 , H01J3/00
CPC分类号： H04L29/06 , H04L69/32
摘要： A network input/output processing system for sending and receiving messages between a large scale computer system and associated communications networks. Executive operating system services provide access to a control table, an input queue, and an output queue stored in the computer system's main memory. A network input/output processor responds to requests by application programs, through a communications program, for receiving input from and sending output to a network, concurrently with requests to communicate with directly attached peripheral devices such as disk drives, tape drives, and printers. The network input/output processor receives initialization, reset, and termination requests via the control table. Requests to receive input are received from the input queue. Input data is stored into buffers as directed by the input request. Requests to send output are received from the output queue. Output data is read from the buffers as directed by the output request. Executive operating system services provide for control of input data transfers and output data transfers. Special purpose Instruction Processor instructions provide the capability to build control programs for processing input and output messages used by the network input/output processor to effect message transfers, thereby minimizing host instruction pathlength for communications I/O. The system architecture minimizes internal data copy between processes by using transferable buffers as communications buffers.
摘要翻译：一种用于在大规模计算机系统和相关联的通信网络之间发送和接收消息的网络输入/输出处理系统。执行操作系统服务提供对存储在计算机系统的主存储器中的控制表，输入队列和输出队列的访问。网络输入/输出处理器通过通信程序响应于应用程序的请求，用于从与网络接收的输入和向网络发送输出，以及与直接连接的外围设备（例如磁盘驱动器，磁带驱动器和打印机）进行通信的请求同时进行。网络输入/输出处理器通过控制表接收初始化，复位和终止请求。从输入队列接收到接收输入的请求。输入数据按输入请求的指示存储到缓冲区中。从输出队列接收请求发送输出。按照输出请求的指示从缓冲区读取输出数据。执行操作系统服务提供对输入数据传输和输出数据传输的控制。特殊用途指令处理器指令提供构建控制程序的能力，用于处理网络输入/输出处理器使用的输入和输出消息，以实现消息传输，从而最小化通信I / O的主机指令路径长度。系统架构通过使用可传输缓冲区作为通信缓冲区来最小化进程之间的内部数据复制。

2. 发明授权

US06199135B1 Source synchronous transfer scheme for a high speed memory interface 失效
标题翻译：高速存储器接口的源同步传输方案
公开(公告)号：US06199135B1
公开(公告)日：2001-03-06
申请号：US09097287
申请日：1998-06-12
申请人： David A. Maahs , Robert M. Malek , Mitchell A. Bauman
发明人： David A. Maahs , Robert M. Malek , Mitchell A. Bauman
IPC分类号： G06F1342
CPC分类号： G06F13/4243
摘要： Data transfer scheme wherein data transfer rates can be effectively doubled with no increase in the clock speed of the interface. This is accomplished by allowing more than one data transfer to occur on a single clock cycle. This transfer scheme increases the transfer rate of the interface by multiplexing two data groups on the same interface. These data groups are transmitted from a source phase latch at approximately the same time as two strobe signals which have low skew with respect to the data. The master and slave strobe signals are logically combined to create an even latch enable signal and an odd latch enable signal that are used to latch and de-multiplex the multiplexed data groups at a receiving end of a pair of flow-though source synchronous latches.
摘要翻译：数据传输方案，其中数据传输速率可以有效地加倍，而接口的时钟速度没有增加。这是通过允许在单个时钟周期上发生多个数据传输来实现的。该传输方案通过在同一接口上复用两个数据组来提高接口的传输速率。这些数据组与源相位锁存器以大约相同的时间从相对于数据具有低偏移的两个选通信号发送。主和从选通信号在逻辑上组合以产生用于在一对流通源同步锁存器的接收端处锁存和解复用多路复用数据组的偶锁存使能信号和奇数锁存使能信号。

3. 发明授权

US10824748B2 Method and system for low overhead control/status handshake for remote shared file server 有权
公开(公告)号：US10824748B2
公开(公告)日：2020-11-03
申请号：US15933662
申请日：2018-03-23
申请人： Carl R Crandall , Robert M Malek , Ravi Kumar Rao , Souvik Das , Manish Ranjan Mahanta
发明人： Carl R Crandall , Robert M Malek , Ravi Kumar Rao , Souvik Das , Manish Ranjan Mahanta
IPC分类号： G06F16/17 , G06F21/62 , G06F9/50 , G06F16/11
摘要： A method and system for providing a plurality of host systems shared access to data files from a file server. The method includes monitoring a control file for updates, the control file located within a corresponding host directory located within the file server; receiving a request for access to a data file stored on the file server, the access request being written to the control file, the access request including a requested data file operation; performing the requested data file operation in response to the control file being updated with the access request; creating a status file in the host directory in which the requested data file operation was performed upon completion of the requested data file operation; writing status data in the status file, the status data including a result of the performance of the requested data file operation; and allowing access to the host directory in which the requested data file operation was performed in response to the status data being written to the status file.

4. 发明授权

US5809540A Processor command for prompting a storage controller to write a day clock value to specified memory location 失效
标题翻译：处理器命令，用于提示存储控制器将日期时钟值写入指定的存储位置
公开(公告)号：US5809540A
公开(公告)日：1998-09-15
申请号：US577909
申请日：1995-12-04
申请人： Robert M. Malek , David P. Williams , Stephen Sutter
发明人： Robert M. Malek , David P. Williams , Stephen Sutter
IPC分类号： G06F1/14 , G06F11/34 , G07C1/00
CPC分类号： G06F11/3466 , G06F1/14 , G06F2201/835
摘要： A method and apparatus for efficiently reading a day clock and storing the value into main storage. An advantage is that the memory storage command can request the main storage control to read a current day clock value and store the value into a main storage location specified by the requesting processor while allowing the requesting processor to continue processing other commands. A further advantage is that the requesting processor does not have to wait for the return of a day clock value or the generation of a main storage write request which may reduce the number of main storage I/O bus requests and bus transfer cycles over that normally required to transfer the day clock value to the requesting processor and then back to main storage.
摘要翻译：一种用于有效读取日间时钟并将该值存储到主存储器中的方法和装置。优点是，存储器存储命令可以请求主存储控制器读取当前日期时钟值，并将该值存储到由请求处理器指定的主存储位置中，同时允许请求处理器继续处理其他命令。另一个优点是，请求处理器不必等待日时钟值的返回或主存储写请求的产生，这可以减少主存储I / O总线请求的数量和总线传输周期的数量将日间时钟值传送到请求处理器，然后返回到主存储器。

5. 发明授权

US4546430A Control unit busy queuing 失效
标题翻译：控制单元忙排队
公开(公告)号：US4546430A
公开(公告)日：1985-10-08
申请号：US513051
申请日：1983-07-13
申请人： David J. Moore , Larry L. Byers , Duane G. Kurth , Donald T. Bordsen , John R. Honkomp , Bruce C. Todd , Robert M. Malek
发明人： David J. Moore , Larry L. Byers , Duane G. Kurth , Donald T. Bordsen , John R. Honkomp , Bruce C. Todd , Robert M. Malek
IPC分类号： G06F13/10 , G06F13/12 , G06F13/20 , G06F3/00
CPC分类号： G06F13/20 , G06F13/122
摘要： In a system wherein a central computer complex is connected through central control modules (CCM) and channel modules (CM) to the control units of peripheral subsystems, a first queue is maintained in a CCM for Start I/O Fast (SIOF) commands waiting to be accepted by the CMs connected thereto. After a CM accepts an SIOF command and passes it on to a control unit, the control unit may return to the CM a busy status which is then passed through to the CCM. The CCM maintains a control unit busy (CUB) queue and an entry is made therein when busy status is returned. When a control unit reports control unit end status to the CCM, the CUB queue is linked to the top of the SIOF so that the CMs may again be informed that the SIOF commands are available. The arrangement avoids two interruptions of the central computer complex to report first that the control unit is busy and then that the control unit is available.
摘要翻译：在中央计算机复合体通过中央控制模块（CCM）和信道模块（CM）连接到外围子系统的控制单元的系统中，第一个队列保持在用于启动I / O快速（SIOF）命令等待的CCM中被连接到其的CM接受。在CM接收到SIOF命令并将其传递给控制单元之后，控制单元可以将CM返回到繁忙状态，然后将其传递给CCM。当忙碌状态返回时，CCM维护一个控制单元忙（CUB）队列并进入其中。当控制单元将控制单元的结束状态报告给CCM时，CUB队列被链接到SIOF的顶部，使得CM再次被通知SIOF命令可用。该装置避免中央计算机复合体的两次中断，首先报告控制单元正忙，然后控制单元可用。

6. 发明申请

US20190258810A1 METHOD AND SYSTEM FOR LOW OVERHEAD CONTROL/STATUS HANDSHAKE FOR REMOTE SHARED FILE SERVER 审中-公开
公开(公告)号：US20190258810A1
公开(公告)日：2019-08-22
申请号：US15933662
申请日：2018-03-23
申请人： CARL R. CRANDALL , ROBERT M. MALEK , RAVI KUMAR RAO , SOUVIK DAS , MANISH RANJAN MAHANTA
发明人： CARL R. CRANDALL , ROBERT M. MALEK , RAVI KUMAR RAO , SOUVIK DAS , MANISH RANJAN MAHANTA
IPC分类号： G06F21/62 , G06F17/30 , G06F9/50
摘要： A method and system for providing a plurality of host systems shared access to data files from a file server. The method includes monitoring a control file for updates, the control file located within a corresponding host directory located within the file server; receiving a request for access to a data file stored on the file server, the access request being written to the control file, the access request including a requested data file operation; performing the requested data file operation in response to the control file being updated with the access request; creating a status file in the host directory in which the requested data file operation was performed upon completion of the requested data file operation; writing status data in the status file, the status data including a result of the performance of the requested data file operation; and allowing access to the host directory in which the requested data file operation was performed in response to the status data being written to the status file.

7. 发明授权

US06785775B1 Use of a cache coherency mechanism as a doorbell indicator for input/output hardware queues 有权
标题翻译：使用高速缓存一致性机制作为输入/输出硬件队列的门铃指示器
公开(公告)号：US06785775B1
公开(公告)日：2004-08-31
申请号：US10101407
申请日：2002-03-19
申请人： Robert M. Malek
发明人： Robert M. Malek
IPC分类号： G06F1200
CPC分类号： G06F12/0831
摘要： A method of and apparatus for improving the scheduling efficiency of a data processing system using the facilities which maintain coherency of the system's level cache memories. These efficiencies result from monitoring the cache memory lines which indicate invalidation of a cache memory entry because of a storage operation within backing memory. This invalidity signal is utilized to generate a doorbell type interface indication of a new application entry within the work queue.
摘要翻译：一种用于提高数据处理系统的调度效率的方法和装置，所述数据处理系统使用保持系统级高速缓存存储器的一致性的设施。这些效率是由于监视高速缓冲存储器线，这些高速缓冲存储器线指示高速缓冲存储器条目的无效，这是由于后备存储器中的存储操作。该无效信号用于产生工作队列内新的应用条目的门铃式界面指示。

8. 发明授权

US06697925B1 Use of a cache ownership mechanism to synchronize multiple dayclocks 失效
标题翻译：使用缓存所有权机制来同步多个时钟
公开(公告)号：US06697925B1
公开(公告)日：2004-02-24
申请号：US09748535
申请日：2000-12-22
申请人： James L. Federici , Kelvin S. Vartti , Robert M. Malek , Lewis A. Boone
发明人： James L. Federici , Kelvin S. Vartti , Robert M. Malek , Lewis A. Boone
IPC分类号： G06F1200
CPC分类号： G06F12/0815 , G06F1/14
摘要： A method of and apparatus for improving the efficiency of a data processing system employing multiple dayclocks using the facilities which maintain coherency of the system's level cache memories. These efficiencies result from dedicating a separate individual dayclock to each of the multiple instruction processors within the data processing system thereby decreasing access time and user queuing. These individual dayclocks are each incremented at one microsecond intervals. However, these individual dayclocks require periodic synchronization to avoid system level time-tagging problems. This synchronization occurs at 20 microsecond intervals using the cache coherency maintenance hardware of the system.
摘要翻译：一种使用保持系统级高速缓冲存储器的一致性的设施来提高使用多个时钟的数据处理系统的效率的方法和装置。这些效率是由专用于数据处理系统中的多个指令处理器的每一个单独的时钟而导致的，从而减少访问时间和用户排队。这些单独的日钟分别以1微秒的间隔递增。然而，这些单独的时钟需要定期同步以避免系统级时间标记问题。该同步使用系统的高速缓存一致性维护硬件以20微秒的间隔进行。

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