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1. 发明授权

US08803630B2 Miniaturized wide-band baluns for RF applications 有权
公开(公告)号：US08803630B2
公开(公告)日：2014-08-12
申请号：US12579299
申请日：2009-10-14
申请人： Kai Liu , Robert Charles Frye
发明人： Kai Liu , Robert Charles Frye
IPC分类号： H03H7/42 , H01P3/08 , H01F17/00
CPC分类号： H03H7/42 , H01F17/0013 , H03H7/1775 , Y10T29/4902 , Y10T29/49071
摘要： A wide-band balun device includes a first metallization deposited over a substrate and oriented in a first coil. The first coil extends horizontally across the substrate while maintaining a substantially flat vertical profile. A second metallization is deposited over the substrate and oriented in a second coil. The second coil is magnetically coupled to the first coil and a portion of the second coil oriented interiorly of the first coil. A third metallization is deposited over the substrate and oriented in a third coil. The third coil is magnetically coupled to the first and second coils. A first portion of the third coil is oriented interiorly of the second coil. The third coil has a balanced port connected to the third coil between second and third portions of the third coil.

2. 发明授权

US08669637B2 Integrated passive device system 有权
标题翻译：集成无源器件系统
公开(公告)号：US08669637B2
公开(公告)日：2014-03-11
申请号：US11553949
申请日：2006-10-27
申请人： Yaojian Lin , Haijing Cao , Robert Charles Frye , Pandi Chelvam Marimuthu
发明人： Yaojian Lin , Haijing Cao , Robert Charles Frye , Pandi Chelvam Marimuthu
IPC分类号： H01L27/01
CPC分类号： H01L23/66 , H01L23/50 , H01L2224/05001 , H01L2224/05023 , H01L2224/05027 , H01L2224/05572 , H01L2224/05647 , H01L2224/05671 , H01L2224/13 , H01L2924/1305 , H01L2924/19011 , H01L2924/00 , H01L2924/00014
摘要： An integrated passive device system is disclosed including forming a first dielectric layer over a semiconductor substrate, depositing a metal capacitor layer on the first dielectric layer, forming a second dielectric layer over the metal capacitor layer, and depositing a metal layer over the second dielectric layer for forming the integrated capacitor, an integrated resistor, an integrated inductor, or a combination thereof.
摘要翻译：公开了一种集成的无源器件系统，包括在半导体衬底上形成第一介电层，在第一电介质层上沉积金属电容器层，在金属电容器层上形成第二电介质层，以及在第二电介质层上沉积金属层用于形成集成电容器，集成电阻器，集成电感器或其组合。

3. 发明授权

US08111113B2 Semiconductor device and method of forming thin film capacitor 有权
标题翻译：半导体器件和薄膜电容器的形成方法
公开(公告)号：US08111113B2
公开(公告)日：2012-02-07
申请号：US12705810
申请日：2010-02-15
申请人： Kai Liu , Robert Charles Frye
发明人： Kai Liu , Robert Charles Frye
IPC分类号： H03H7/00 , H01G4/06
CPC分类号： H03H7/09 , H01F17/0006 , H01F2017/0046 , H01F2017/0073 , H03H7/1708 , H03H7/1775 , Y10T29/4902
摘要： A semiconductor device has a first coil structure formed over the substrate. A second coil structure is formed over the substrate adjacent to the first coil structure. A third coil structure is formed over the substrate adjacent to the second coil structure. The first and second coil structures are coupled by mutual inductance, and the second and third coil structures are coupled by mutual inductance. The first, second, and third coil structures each have a height greater than a skin current depth of the coil structure defined as a depth which current reduces to 1/(complex permittivity) of a surface current value. A thin film capacitor is formed within the semiconductor device by a first metal plate, dielectric layer over the first metal plate, and second and third electrically isolated metal plates opposite the first metal plate. The terminals are located on the same side of the capacitor.
摘要翻译：半导体器件具有形成在衬底上的第一线圈结构。在与第一线圈结构相邻的衬底上形成第二线圈结构。在与第二线圈结构相邻的衬底上形成第三线圈结构。第一和第二线圈结构通过互感耦合，并且第二和第三线圈结构通过互感耦合。第一，第二和第三线圈结构各自具有高于线圈结构的皮肤电流深度的高度，其被定义为电流减小到表面电流值的1 /（复数介电常数）的深度。通过第一金属板，第一金属板上的电介质层和与第一金属板相对的第二和第三电隔离金属板，在半导体器件内形成薄膜电容器。端子位于电容器的同一侧。

4. 发明申请

US20100200951A1 Method of Forming Top Electrode for Capacitor and Interconnection in Integrated Passive Device (IPD) 有权
标题翻译：在集成无源器件（IPD）中形成电容器和互连顶电极的方法
公开(公告)号：US20100200951A1
公开(公告)日：2010-08-12
申请号：US12763386
申请日：2010-04-20
申请人： Yaojian Lin , Robert Charles Frye
发明人： Yaojian Lin , Robert Charles Frye
IPC分类号： H01L23/522
CPC分类号： H01L28/40 , H01L23/5223 , H01L24/05 , H01L24/13 , H01L2224/0401 , H01L2924/01079 , H01L2924/14 , H01L2924/19011 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/30105
摘要： A method of manufacturing a semiconductor device includes providing a substrate having a first conductive layer disposed on a top surface of the substrate. A high resistivity layer is formed over the substrate and the first conductive layer. A dielectric layer is deposited over the substrate, first conductive layer and high resistivity layer. A portion of the dielectric layer, high resistivity layer, and first conductive layer forms a capacitor stack. A first passivation layer is formed over the dielectric layer. A second conductive layer is formed over the capacitor stack and a portion of the first passivation layer. A first opening is etched in the dielectric layer to expose a surface of the high resistivity layer. A third and fourth conductive layer is deposited over the first opening in the dielectric layer and a portion of the first passivation layer.
摘要翻译：一种制造半导体器件的方法包括提供具有设置在基板的顶表面上的第一导电层的基板。在基板和第一导电层上形成高电阻率层。介电层沉积在衬底，第一导电层和高电阻率层上。介电层，高电阻率层和第一导电层的一部分形成电容器叠层。在电介质层上形成第一钝化层。在电容器堆叠和第一钝化层的一部分上形成第二导电层。在电介质层中蚀刻第一开口以暴露高电阻率层的表面。在电介质层中的第一开口和第一钝化层的一部分上沉积第三和第四导电层。

5. 发明授权

US06282100B1 Low cost ball grid array package 有权
标题翻译：低成本球栅阵列封装
公开(公告)号：US06282100B1
公开(公告)日：2001-08-28
申请号：US09346100
申请日：1999-07-01
申请人： Yinon Degani , Thomas Dixon Dudderar , Robert Charles Frye
发明人： Yinon Degani , Thomas Dixon Dudderar , Robert Charles Frye
IPC分类号： H05K118
CPC分类号： H01L23/49833 , H01L24/45 , H01L24/48 , H01L25/0657 , H01L2224/16145 , H01L2224/45144 , H01L2224/48091 , H01L2224/48227 , H01L2225/0651 , H01L2225/06517 , H01L2225/06572 , H01L2225/06586 , H01L2924/01079 , H01L2924/10253 , H01L2924/14 , H01L2924/00014 , H01L2924/00
摘要： The specification describes a high density I/O IC package in which the IC chip is bonded to a silicon intermediate interconnection substrate (IIS), and the IIS is wire bonded to a printed wiring board. This marriage of wire bond technology with high density I/O IC chips results in a low cost, high reliability, state of the art IC package.
摘要翻译：该说明书描述了IC芯片与硅中间互连基板（IIS）接合的高密度I / O IC封装，并且IIS被引线接合到印刷电路板。这种线接技术与高密度I / O IC芯片的结合导致低成本，高可靠性，最先进的IC封装。

6. 发明申请

US20100140742A1 Semiconductor Device and Method of Forming Thin Film Capacitor 有权
标题翻译：半导体器件和薄膜电容器的形成方法
公开(公告)号：US20100140742A1
公开(公告)日：2010-06-10
申请号：US12705810
申请日：2010-02-15
申请人： Kai Liu , Robert Charles Frye
发明人： Kai Liu , Robert Charles Frye
IPC分类号： H01L29/92 , H01L21/02
CPC分类号： H03H7/09 , H01F17/0006 , H01F2017/0046 , H01F2017/0073 , H03H7/1708 , H03H7/1775 , Y10T29/4902
摘要： A semiconductor device has a first coil structure formed over the substrate. A second coil structure is formed over the substrate adjacent to the first coil structure. A third coil structure is formed over the substrate adjacent to the second coil structure. The first and second coil structures are coupled by mutual inductance, and the second and third coil structures are coupled by mutual inductance. The first, second, and third coil structures each have a height greater than a skin current depth of the coil structure defined as a depth which current reduces to 1/(complex permittivity) of a surface current value. A thin film capacitor is formed within the semiconductor device by a first metal plate, dielectric layer over the first metal plate, and second and third electrically isolated metal plates opposite the first metal plate. The terminals are located on the same side of the capacitor.
摘要翻译：半导体器件具有形成在衬底上的第一线圈结构。在与第一线圈结构相邻的衬底上形成第二线圈结构。在与第二线圈结构相邻的衬底上形成第三线圈结构。第一和第二线圈结构通过互感耦合，并且第二和第三线圈结构通过互感耦合。第一，第二和第三线圈结构各自具有高于线圈结构的皮肤电流深度的高度，其被定义为电流减小到表面电流值的1 /（复数介电常数）的深度。通过第一金属板，第一金属板上的电介质层和与第一金属板相对的第二和第三电隔离金属板，在半导体器件内形成薄膜电容器。端子位于电容器的同一侧。

7. 发明申请

US20100045398A1 Miniaturized Wide-Band Baluns for RF Applications 有权
公开(公告)号：US20100045398A1
公开(公告)日：2010-02-25
申请号：US12606351
申请日：2009-10-27
申请人： Kai Liu , Robert Charles Frye
发明人： Kai Liu , Robert Charles Frye
IPC分类号： H03H7/42 , H01F41/00
CPC分类号： H03H7/42 , H01F17/0013 , H03H7/1775 , Y10T29/4902 , Y10T29/49071
摘要： A wide-band balun device includes a first metallization deposited over a substrate and oriented in a first coil. The first coil extends horizontally across the substrate while maintaining a substantially flat vertical profile. A second metallization is deposited over the substrate and oriented in a second coil. The second coil is magnetically coupled to the first coil and a portion of the second coil oriented interiorly of the first coil. A third metallization is deposited over the substrate and oriented in a third coil. The third coil is magnetically coupled to the first and second coils. A first portion of the third coil is oriented interiorly of the second coil. The third coil has a balanced port connected to the third coil between second and third portions of the third coil.

8. 发明申请

US20100039185A1 Miniaturized Wide-Band Baluns for RF Applications 有权
标题翻译：用于射频应用的小型化宽带不平衡变压器
公开(公告)号：US20100039185A1
公开(公告)日：2010-02-18
申请号：US12579286
申请日：2009-10-14
申请人： Kai Liu , Robert Charles Frye
发明人： Kai Liu , Robert Charles Frye
IPC分类号： H03H5/12
CPC分类号： H03H7/42 , H01F17/0013 , H03H7/1775 , Y10T29/4902 , Y10T29/49071
摘要： A wide-band balun device includes a first metallization deposited over a substrate and oriented in a first coil. The first coil extends horizontally across the substrate while maintaining a substantially flat vertical profile. A second metallization is deposited over the substrate and oriented in a second coil. The second coil is magnetically coupled to the first coil and a portion of the second coil oriented interiorly of the first coil. A third metallization is deposited over the substrate and oriented in a third coil. The third coil is magnetically coupled to the first and second coils. A first portion of the third coil is oriented interiorly of the second coil. The third coil has a balanced port connected to the third coil between second and third portions of the third coil.
摘要翻译：宽带平衡 - 不平衡转换器包括沉积在衬底上并定向在第一线圈中的第一金属化。第一线圈水平延伸穿过衬底，同时保持基本平坦的垂直轮廓。第二金属化沉积在衬底上并定向在第二线圈中。第二线圈磁耦合到第一线圈，并且第二线圈的一部分定向在第一线圈的内部。第三金属化沉积在衬底上并定向在第三线圈中。第三线圈磁耦合到第一和第二线圈。第三线圈的第一部分位于第二线圈的内部。第三线圈具有在第三线圈的第二和第三部分之间连接到第三线圈的平衡端口。

9. 发明申请

US20080233731A1 Method of Forming Top Electrode for Capacitor and Interconnection in Integrated Passive Device (IPD) 有权
标题翻译：在集成无源器件（IPD）中形成电容器和互连顶电极的方法
公开(公告)号：US20080233731A1
公开(公告)日：2008-09-25
申请号：US11689319
申请日：2007-03-21
申请人： Yaojian LIN , Robert Charles FRYE
发明人： Yaojian LIN , Robert Charles FRYE
IPC分类号： H01L21/44
CPC分类号： H01L28/40 , H01L23/5223 , H01L24/05 , H01L24/13 , H01L2224/0401 , H01L2924/01079 , H01L2924/14 , H01L2924/19011 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/30105
摘要： A method of manufacturing a semiconductor device includes providing a substrate having a first conductive layer disposed on a top surface of the substrate. A high resistivity layer is formed over the substrate and the first conductive layer. A dielectric layer is deposited over the substrate, first conductive layer and high resistivity layer. A portion of the dielectric layer, high resistivity layer, and first conductive layer forms a capacitor stack. A first passivation layer is formed over the dielectric layer. A second conductive layer is formed over the capacitor stack and a portion of the first passivation layer. A first opening is etched in the dielectric layer to expose a surface of the high resistivity layer. A third and fourth conductive layer is deposited over the first opening in the dielectric layer and a portion of the first passivation layer.
摘要翻译：一种制造半导体器件的方法包括提供具有设置在基板的顶表面上的第一导电层的基板。在基板和第一导电层上形成高电阻率层。介电层沉积在衬底，第一导电层和高电阻率层上。介电层，高电阻率层和第一导电层的一部分形成电容器叠层。在电介质层上形成第一钝化层。在电容器堆叠和第一钝化层的一部分上形成第二导电层。在电介质层中蚀刻第一开口以暴露高电阻率层的表面。在电介质层中的第一开口和第一钝化层的一部分上沉积第三和第四导电层。

10. 发明授权

US07061340B2 Differently-tuned VCO using inductively coupled varactors 有权
标题翻译：使用电感耦合变容二极管的不同调谐VCO
公开(公告)号：US07061340B2
公开(公告)日：2006-06-13
申请号：US10816280
申请日：2004-04-01
申请人： Vito Boccuzzi , Robert Charles Frye , Sander Lauentius Gierkink
发明人： Vito Boccuzzi , Robert Charles Frye , Sander Lauentius Gierkink
IPC分类号： H03B1/00
CPC分类号： H03B5/1228 , H03B5/1215 , H03B5/1253 , H03B5/1256 , H03B5/1265 , H03B5/1293 , H03B5/1296 , H03B2201/0208
摘要： A differently-tuned voltage controlled oscillator (VCO) and its application in a multi-band VCO tuner are disclosed. In one aspect of the invention, the VCO comprises a plurality of serially connected inductive elements each including inductively coupled inductor elements, a varactor element connected in parallel with the serially connected first inductor elements and means to apply a first and second tuning voltage to elements of the varactor element. In a second aspect, the VCO further comprises a second varactor element connected in parallel with the inductive elements, and means to apply the second tuning voltage elements of the second varactor element.
摘要翻译：公开了一种不同调谐的压控振荡器（VCO）及其在多频带VCO调谐器中的应用。在本发明的一个方面，VCO包括多个串联连接的电感元件，每个电感元件包括电感耦合电感器元件，与串联连接的第一电感器元件并联连接的变容二极管元件和将第一和第二调谐电压施加到变形元件。在第二方面，VCO还包括与感应元件并联连接的第二变容二极管元件，以及施加第二变容二极管元件的第二调谐电压元件的装置。

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