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1. 发明授权

US07290127B2 System and method of remotely initializing a local processor 失效
标题翻译：远程初始化本地处理器的系统和方法
公开(公告)号：US07290127B2
公开(公告)日：2007-10-30
申请号：US10032762
申请日：2001-12-26
申请人： Mark A Schmisseur , Timothy J Jehl , Richard P Mackey , Delf Atallah
发明人： Mark A Schmisseur , Timothy J Jehl , Richard P Mackey , Delf Atallah
IPC分类号： G06F15/177
CPC分类号： G06F1/24
摘要： A system and method of initializing a core processing circuit are disclosed. The core processing circuit is held in a reset state while a reset vector is loaded to one or more registers at a boot address associated with the core processing circuit. The reset vector is loaded from a system memory through a host bridge. The reset vector comprises one or more instructions to initialize the core processing system upon release from a reset state.
摘要翻译：公开了一种初始化核心处理电路的系统和方法。核心处理电路被保持在复位状态，而复位向量被加载到与核心处理电路相关联的引导地址的一个或多个寄存器。复位向量通过主机桥从系统存储器加载。复位向量包括在从复位状态释放时初始化核心处理系统的一个或多个指令。

2. 发明授权

US07130933B2 Method, system, and program for handling input/output commands 有权
标题翻译：用于处理输入/输出命令的方法，系统和程序
公开(公告)号：US07130933B2
公开(公告)日：2006-10-31
申请号：US10205663
申请日：2002-07-24
申请人： Sailesh Bissessur , Richard P. Mackey , Mark A. Schmisseur , David R. Smith
发明人： Sailesh Bissessur , Richard P. Mackey , Mark A. Schmisseur , David R. Smith
IPC分类号： G06F13/28
CPC分类号： G06F13/28
摘要： Provided are a method, system, and program for handling Input/Output (I/O) requests. A bus enables communication with an initiator, target device and device controller, wherein the device controller accesses the target device to execute I/O commands directed to the target device. An I/O request command is received to access the target device. The initiator is configured to transmit at least one data request on the bus to one memory address in a predefined address window of the device controller. The device controller is enabled to claim the data request to the memory address in the predefined address window from the initiator on the bus to execute the data request against the target device.
摘要翻译：提供了一种用于处理输入/输出（I / O）请求的方法，系统和程序。总线使得能够与发起者，目标设备和设备控制器进行通信，其中设备控制器访问目标设备以执行指向目标设备的I / O命令。接收到I / O请求命令以访问目标设备。启动器被配置为将总线上的至少一个数据请求发送到设备控制器的预定义地址窗口中的一个存储器地址。设备控制器被允许从总线上的启动器向预定义的地址窗口中的存储器地址提出数据请求，以针对目标设备执行数据请求。

3. 发明授权

US07000146B2 Power loss memory back-up 失效
公开(公告)号：US07000146B2
公开(公告)日：2006-02-14
申请号：US09872872
申请日：2001-05-31
申请人： Richard P. Mackey , Richard P. Luckett , James D. Warren , Sailesh Bissessur
发明人： Richard P. Mackey , Richard P. Luckett , James D. Warren , Sailesh Bissessur
IPC分类号： G06F11/00
CPC分类号： G06F1/30 , G06F1/24
摘要： A memory system provides one or more control signals for configuring and controlling a memory sub-system during a power failure or system reset. A power delay circuit and a power fail controller cooperate to quickly place the memory system in a retention state in the event a power failure event is detected. The power delay circuit detects either a reset signal or power failure to initiate the memory retention state. The power delay circuit and power fail controller ensure the memory system is initialized prior to entering the retention state.

4. 发明授权

US06460108B1 Low cost data streaming mechanism 有权
标题翻译：低成本数据流传输机制
公开(公告)号：US06460108B1
公开(公告)日：2002-10-01
申请号：US09282386
申请日：1999-03-31
申请人： Jeff J. McCoskey , Richard P. Mackey , Barry R. Davis
发明人： Jeff J. McCoskey , Richard P. Mackey , Barry R. Davis
IPC分类号： G06F1300
CPC分类号： G06F13/4059
摘要： A method and apparatus for providing an efficient, low cost data streaming mechanism from a first bus architecture to a second bus architecture across a bus bridge. Separate read and write data queues are provided in the bus bridge for transfer of data in both directions, and the speed of one of the buses is increased over the speed of the other one of the buses. In one embodiment, the first bus is a PCI bus and the second bus is an internal CPU bus.
摘要翻译：一种用于在总线桥上从第一总线架构向第二总线架构提供有效的低成本数据流机制的方法和装置。在总线桥中提供单独的读写数据队列，用于在两个方向上传输数据，其中一条总线的速度在另一条总线的速度上增加。在一个实施例中，第一总线是PCI总线，第二总线是内部CPU总线。

5. 发明授权

US07263571B2 Bus segment decoder 有权
标题翻译：总线段解码器
公开(公告)号：US07263571B2
公开(公告)日：2007-08-28
申请号：US11418600
申请日：2006-05-05
申请人： Richard P. Mackey
发明人： Richard P. Mackey
IPC分类号： G06F13/36 , G06F13/00
CPC分类号： G06F13/4027
摘要： Disclosed are a system and method of forwarding bus transactions from a source device to a target device in multiple data bus environment. A bridge is coupled between a first data bus and a second data bus while a target device is coupled to the first data bus at a data bus address. A decoder may provide bus segment information to the bridge independently of a bus transaction on the second data bus initiated by a source device. The bridge may comprise logic to forward the bus transaction on the first data bus to the target device based upon the bus segment information.
摘要翻译：公开了一种在多个数据总线环境中将总线事务从源设备转发到目标设备的系统和方法。当目标设备在数据总线地址处耦合到第一数据总线时，桥耦合在第一数据总线和第二数据总线之间。解码器可以独立于由源设备发起的第二数据总线上的总线事务向桥提供总线段信息。桥可以包括基于总线段信息将第一数据总线上的总线事务转发到目标设备的逻辑。

6. 发明授权

US07123674B2 Reducing latency and power in asynchronous data transfers 有权
公开(公告)号：US07123674B2
公开(公告)日：2006-10-17
申请号：US09872277
申请日：2001-05-31
申请人： Richard P. Mackey , David R. Smith , Jeffrey J. McCoskey
发明人： Richard P. Mackey , David R. Smith , Jeffrey J. McCoskey
IPC分类号： H04L7/00
CPC分类号： H04L7/0012 , G06F1/32 , H04L7/0045
摘要： Reducing latency and power in the transfer of data between a source and destination domain involves the production of a source-enable signal base on a synchronous-pulse signal. The source-enable signal operates to enable a source register to capture data from a source domain. The source-enable signal may be controlled by a source-inhibit signal. The source-inhibit signal prevents the synchronous-pulse signal from producing the source enable signal and capture clock until data is available for transmission.

7. 发明授权

US07080187B2 Bug segment decoder 失效
标题翻译： Bug段解码器
公开(公告)号：US07080187B2
公开(公告)日：2006-07-18
申请号：US10028881
申请日：2001-12-20
申请人： Richard P. Mackey
发明人： Richard P. Mackey
IPC分类号： G06F3/00 , G06F13/28 , G06F13/36
CPC分类号： G06F13/4027
摘要： Disclosed are a system and method of forwarding bus transactions from a source device to a target device in multiple data bus enviroment. A bridge is coupled between a first data bus and a second data bus while a target device is coupled to the first data bus at a data bus address. A decoder may provide bus segment information to the bridge independently of a bus transaction on the second data bus initiated by a source device. The bridge may comprise logic to forward the bus transaction on the first data bus to the target device based upon the bus segment information.
摘要翻译：公开了一种在多个数据总线环境中将总线事务从源设备转发到目标设备的系统和方法。当目标设备在数据总线地址处耦合到第一数据总线时，桥耦合在第一数据总线和第二数据总线之间。解码器可以独立于由源设备发起的第二数据总线上的总线事务向桥提供总线段信息。桥可以包括基于总线段信息将第一数据总线上的总线事务转发到目标设备的逻辑。

8. 发明授权

US07509559B2 Apparatus and method for parity generation in a data-packing device 失效
标题翻译：数据包装装置中奇偶生成的装置和方法
公开(公告)号：US07509559B2
公开(公告)日：2009-03-24
申请号：US11171086
申请日：2005-06-27
申请人： Richard P. Mackey
发明人： Richard P. Mackey
IPC分类号： H03M13/00
CPC分类号： G06F11/1008 , G06F11/108
摘要： A data-packing device, such as a direct memory access controller (DMA), aligns data at a granularity smaller than an error protected unit (EPU) encoded by an error correction code (ECC) in the memory. For example, the data alignment is at a double-word level or a byte level. The data-packing device reads data from the memory, shifting the data, and marks a good data unit as corrupted if the data unit constitutes a fractional portion of a corrupted EPU. The marking of the data unit is performed by inverting a parity bit of the data unit.
摘要翻译：诸如直接存储器存取控制器（DMA）的数据打包装置将数据以小于由存储器中的纠错码（ECC）编码的错误保护单元（EPU）的粒度对齐。例如，数据对齐是双字级或字节级。数据包装设备从存储器中读取数据，移动数据，并且如果数据单元构成损坏的EPU的分数部分，则将良好的数据单元标记为损坏。通过反转数据单元的奇偶校验位来执行数据单元的标记。

9. 发明授权

US07464199B2 Method, system, and program for handling Input/Output commands 有权
标题翻译：用于处理输入/输出命令的方法，系统和程序
公开(公告)号：US07464199B2
公开(公告)日：2008-12-09
申请号：US11279086
申请日：2006-04-07
申请人： Sailesh Bissessur , Richard P. Mackey , Mark A. Schmisseur , David R. Smith
发明人： Sailesh Bissessur , Richard P. Mackey , Mark A. Schmisseur , David R. Smith
IPC分类号： G06F13/28
CPC分类号： G06F13/28
摘要： Provided are a method, system, and program for handling Input/Output (I/O) requests. A bus enables communication with an initiator, target device and device controller, wherein the device controller accesses the target device to execute I/O commands directed to the target device. An I/O request command is received to access the target device. The initiator is configured to transmit at least one data request on the bus to one memory address in a predefined address window of the device controller. The device controller is enabled to claim the data request to the memory address in the predefined address window from the initiator on the bus to execute the data request against the target device.
摘要翻译：提供了一种用于处理输入/输出（I / O）请求的方法，系统和程序。总线使得能够与发起者，目标设备和设备控制器进行通信，其中设备控制器访问目标设备以执行指向目标设备的I / O命令。接收到I / O请求命令以访问目标设备。启动器被配置为将总线上的至少一个数据请求发送到设备控制器的预定义地址窗口中的一个存储器地址。设备控制器被允许从总线上的启动器向预定义的地址窗口中的存储器地址提出数据请求，以针对目标设备执行数据请求。

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