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1. 发明授权

US4394731A Cache storage line shareability control for a multiprocessor system 失效
标题翻译：多处理器系统的缓存存储线可共享性控制
公开(公告)号：US4394731A
公开(公告)日：1983-07-19
申请号：US205500
申请日：1980-11-10
申请人： Frederick O. Flusche , Richard N. Gustafson , Bruce L. McGilvray
发明人： Frederick O. Flusche , Richard N. Gustafson , Bruce L. McGilvray
IPC分类号： G06F12/08 , G06F15/16
CPC分类号： G06F12/0815
摘要： A multiprocessor (MP) system is described having central processors (CPs) in which each CP has a store-in-cache (SIC) with an associated processor directory (PD). Each PD has a plurality of line entries which define the content of corresponding line positions in the associated SIC. Each line entry has an associated data shareability control bit, designated EX, which may be set to a one or zero state to indicate, respectively, the exclusive (EX) or readonly (RO) state of the associated line. An exclusive line is not shareable, but a readonly line is shareable i.e. may exist validly in more than one SIC in the MP. Any CP in the MP can request data in an EX state from its SIC, which data may or may not be found in its SIC or in another CP's SIC. If a CP requests a line of storage data in EX state and the line is found in EX state in another CP's SIC, it may be allowed to remain in the other CP's SIC by being set to RO state in both CPU SICs for the situations in which: (1) the line is found unchanged in EX state in the other CP's SIC, or (2) the line is found in RO state in the other CP's SIC, in which case the line is received and set to RO state in the requesting SIC even though requested in EX state. But if the line is found to be changed in the other CP's SIC, its shareability designation in the requesting SIC will be EX and the line is invalidated in the other CP's SIC from where it is castout.
摘要翻译：描述了具有中央处理器（CP）的多处理器（MP）系统，其中每个CP具有与相关联的处理器目录（PD）的高速缓存存储器（SIC）。每个PD具有多个行条目，其定义相关SIC中相应行位置的内容。每个行条目具有指定为EX的相关联的数据共享性控制位，其可以被设置为一个或零个状态，以分别指示相关行的排他（EX）或只读（RO）状态。独占行不可共享，但只读行可共享，即可以在MP中的多个SIC中有效存在。 MP中的任何CP可以从其SIC请求EX状态的数据，哪些数据可能在其SIC或另一个CP的SIC中可能找到。如果CP在EX状态下请求一行存储数据，并且在另一个CP的SIC中在EX状态下发现该行，则可以通过在两个CPU SIC中的情况下将其设置为RO状态来保留在其他CP的SIC中其中：（1）其他CP的SIC在EX状态下发现该行不变，或者（2）在另一个CP的SIC中发现该行在RO状态，在这种情况下，该行被接收并设置为RO状态即使在EX状态下请求SIC请求。但是，如果在其他CP的SIC中发现该行已被更改，则其请求的SIC中的可共享性指定将为EX，并且该线在其它CP的SIC中被放弃。

2. 发明授权

US5504859A Data processor with enhanced error recovery 失效
标题翻译：具有增强的错误恢复的数据处理器
公开(公告)号：US5504859A
公开(公告)日：1996-04-02
申请号：US149260
申请日：1993-11-09
申请人： Richard N. Gustafson , John S. Liptay , Charles F. Webb
发明人： Richard N. Gustafson , John S. Liptay , Charles F. Webb
IPC分类号： G06F11/10 , G06F11/14 , G06F11/16
CPC分类号： G06F11/1654 , G06F11/10 , G06F11/1008 , G06F11/1076 , G06F11/1407 , G06F11/1641 , G06F11/165
摘要： Error detection and recovery is provided in a processor of small size and which can be integrated on a single chip by providing buffers for both data and processor status codes in order to contain errors until a subsequent check point preferably generated at the termination of each instruction is reached without detection of an error. Retry of an instruction can therefore be initiated using the status and data validated at the termination of the previous check point and without placing error correction processing in any critical path of the processor. Error detection is accomplished by comparing outputs of at least a pair of unchecked processors for both memory access requests and output data and status codes. Input to the processors is subjected to a parity check and parity check bits are generated for memory access requests. Error correcting codes are generated for data and status codes to allow correction of single bit errors during transmission within the processor or at a storage system. When an error is detected, all data which has not been validated, preferably by changing the logical value of a flag bit associated with each code, at the most recently generated check point is erased. Data codes in which the flag bit has been changed may be transferred to a storage system autonomously even after an error has occurred.
摘要翻译：在小尺寸的处理器中提供错误检测和恢复，并且可以通过为数据和处理器状态代码提供缓冲器来集成在单个芯片上，以便包含错误，直到在每个指令的终止时优选地生成的后续检查点为到达没有检测到错误。因此，可以使用在先前检查点终止时验证的状态和数据来启动指令的重试，并且不在处理器的任何关键路径中进行纠错处理。通过比较两个存储器访问请求和输出数据和状态代码的至少一对未检查处理器的输出来实现错误检测。对处理器的输入进行奇偶校验，并为存储器访问请求生成奇偶校验位。为数据和状态代码生成纠错码，以允许在处理器或存储系统内的传输期间校正单个位错误。当检测到错误时，擦除最近生成的检查点的所有未被验证的数据，优选地通过改变与每个代码相关联的标志位的逻辑值。即使在发生错误之后，标志位已被改变的数据代码也可以被自动地传送到存储系统。

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