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1. 发明授权

US06097401A Integrated graphics processor having a block transfer engine for automatic graphic operations in a graphics system 失效
标题翻译：具有用于在图形系统中自动图形操作的块传送引擎的集成图形处理器
公开(公告)号：US06097401A
公开(公告)日：2000-08-01
申请号：US984183
申请日：1997-11-26
申请人： Richard Charles Andrew Owen , Karl Scott Mills , Bradley Andrew May , Lauren Emory Linstad
发明人： Richard Charles Andrew Owen , Karl Scott Mills , Bradley Andrew May , Lauren Emory Linstad
IPC分类号： G06F9/38 , G06F3/14 , G06F3/153 , G06T1/20 , G09G5/00 , G09G5/36 , G09G5/393 , G06F15/16
CPC分类号： G09G5/393 , G06F3/14 , G09G5/363
摘要： The present invention discloses methods and apparatus for implementing automatic graphics operations with selectable triggering mechanism. One mechanism is hardware related, using the vertical counter in the video control section of the graphics processor. The other mechanism is software related, using the host to directly command the graphics processor. The graphics operations are specified in the header file written by the host in the frame buffer memory. Several header files can be chained together to form a sequence of header files corresponding to very complex graphics operations. Automatic graphics operations, therefore, can be completed without further host intervention resulting in powerful graphics, video, and animation performance.
摘要翻译：本发明公开了利用可选触发机制实现自动图形操作的方法和装置。一种机制是硬件相关的，在图形处理器的视频控制部分使用垂直计数器。另一种机制是软件相关的，使用主机直接命令图形处理器。图形操作在主机在帧缓冲存储器中写入的头文件中指定。可以将几个头文件链接在一起以形成与非常复杂的图形操作相对应的头文件序列。因此，自动图形操作可以在没有进一步的主机干预的情况下完成，从而导致强大的图形，视频和动画性能。

2. 发明授权

US5929837A Method and apparatus for determining representative chrominance components 失效
标题翻译：用于确定代表性色度分量的方法和装置
公开(公告)号：US5929837A
公开(公告)日：1999-07-27
申请号：US107579
申请日：1998-03-02
申请人： Vernon Dennis Hasz , Karl Scott Mills , Richard Charles Andrew Owen , Mark Emil Bonnelycke
发明人： Vernon Dennis Hasz , Karl Scott Mills , Richard Charles Andrew Owen , Mark Emil Bonnelycke
IPC分类号： H04N1/393 , G06T3/40 , G09G5/02 , G09G5/36 , G09G5/39 , H04N9/64 , G09G5/00 , G09G5/04
CPC分类号： G06T3/4007 , G09G5/02 , H04N9/641 , G09G2340/0407
摘要： A method and apparatus for determining representative values for the chrominance components to be associated with a plurality of luminance components in a horizontally shrunken or stretched image for graphics controllers wherein display image data is stored in a buffer memory in a form associating a single set of U and V chrominance components with a plurality of Y luminance values. For a four to one shrinkage of an image in a format associating one set of chrominance components with four pixel luminance values wherein each pixel luminance value in the shrunken image initially has as associated set of chrominance components U.sub.0, U.sub.1, U.sub.2 and U.sub.3 and V.sub.0, V.sub.1, V.sub.2 and V.sub.3, the multiple values of the chrominance components are sequentially accumulated in a 3/4:1/4 ratio in such a manner as to provide an approximate average value for U and V for each set of four pixel luminance values in the shrunken image. Circuitry for processing the chrominance components making use of interpolation circuitry already used for interpolation between pixels for a stretched image is disclosed.
摘要翻译：一种用于确定与图形控制器的水平缩小或拉伸图像中的多个亮度分量相关联的色度分量的代表值的方法和装置，其中显示图像数据以与U单个组合相关联的形式存储在缓冲存储器中和具有多个Y亮度值的V色度分量。对于将一组色度分量与四个像素亮度值相关联的格式的四到一缩小，其中收缩图像中的每个像素亮度值最初具有相关的色度分量U0，U1，U2和U3和V0的集合， V1，V2和V3中，以+ E，fra 3/4 + EE：+ E，fra 1/4 + EE比率顺序地累积色度分量的多个值，以提供近似平均值 U和V对于收缩图像中的每组四个像素亮度值。公开了用于处理使用已经用于拉伸图像的像素之间的插值的插值电路的色度分量的电路。

3. 发明授权

US06563505B1 Method and apparatus for executing commands in a graphics controller chip 失效
标题翻译：用于在图形控制器芯片中执行命令的方法和装置
公开(公告)号：US06563505B1
公开(公告)日：2003-05-13
申请号：US08667826
申请日：1996-06-20
申请人： Karl Scott Mills , Richard Charles Andrew Owen , Mark Emil Bonnelycke
发明人： Karl Scott Mills , Richard Charles Andrew Owen , Mark Emil Bonnelycke
IPC分类号： G06F900
CPC分类号： G09G5/363 , G06F3/14
摘要： A graphics controller circuit for minimizing an amount of data received from a host. The graphics controller circuit includes a register file with a plurality of registers. The graphics controller accepts commands addressed to virtual registers, and generates plurality of instructions including an instruction to access one of the registers in the register file. By using such a virtual register number in a command and generating several instructions in response thereto, the graphics controller circuit of the present invention minimizes the amount of data host sends over the system bus.
摘要翻译：一种用于最小化从主机接收的数据量的图形控制器电路。图形控制器电路包括具有多个寄存器的寄存器文件。图形控制器接受寻址到虚拟寄存器的命令，并且生成多个指令，包括访问寄存器文件中的一个寄存器的指令。通过在命令中使用这样的虚拟寄存器号码并响应于此产生若干指令，本发明的图形控制器电路使主机通过系统总线发送的数据量最小化。

4. 发明授权

US5854620A Method and apparatus for converting monochrome pixel data to color pixel data 失效
标题翻译：将单色像素数据转换为彩色像素数据的方法和装置
公开(公告)号：US5854620A
公开(公告)日：1998-12-29
申请号：US574502
申请日：1995-12-19
申请人： Karl Scott Mills , Jeffrey Michael Holmes , Mark Emil Bonnelycke , Richard Charles Andrew Owen
发明人： Karl Scott Mills , Jeffrey Michael Holmes , Mark Emil Bonnelycke , Richard Charles Andrew Owen
IPC分类号： G06F3/14 , G09G5/02 , G09G5/393 , G09G5/04
CPC分类号： G06F3/14 , G09G5/02 , G09G5/393 , G09G2340/12
摘要： A graphics controller circuit for converting a plurality of monochrome pixel data into a corresponding set of color pixel data in RGB 888 format. The graphics controller circuit packs the converted color pixel data into a plurality of 64-bit color pixel words, with each color pixel word comprising two complete color pixel words and portion of at least one another color pixel word. By having color pixel data cross word boundaries, graphics controller of the present invention optimally stores color pixel data in color pixel words. The graphics controller circuit further includes a half-word addressable split-RAM which enables continuous availability of subsets of monochrome pixel data during each clock cycle for conversion to color data.
摘要翻译：一种图形控制器电路，用于将多个单色像素数据转换成RGB 888格式的相应彩色像素数据组。图形控制器电路将转换的彩色像素数据打包成多个64位彩色像素字，每个彩色像素字包括两个完整的彩色像素字和至少另一个彩色像素字的一部分。通过具有彩色像素数据交叉字边界，本发明的图形控制器以彩色像素字最佳地存储彩色像素数据。图形控制器电路还包括半字可寻址分割RAM，其使得能够在每个时钟周期期间连续可用单色像素数据子集以转换为彩色数据。

5. 发明授权

US5748920A Transaction queue in a graphics controller chip 失效
标题翻译：图形控制器芯片中的事务队列
公开(公告)号：US5748920A
公开(公告)日：1998-05-05
申请号：US536689
申请日：1995-09-29
申请人： Karl Scott Mills , Lauren Emory Linstad , Sherwood Brannon , Mark Emil Bonnelycke , Richard Charles Andrew Owen
发明人： Karl Scott Mills , Lauren Emory Linstad , Sherwood Brannon , Mark Emil Bonnelycke , Richard Charles Andrew Owen
IPC分类号： G06F3/14 , G06F13/00
CPC分类号： G06F3/14
摘要： A transaction queue for transferring data between a host bus and an internal system bus within a graphics controller is disclosed. The queue comprises a First In First Out (FIFO) memory having independent clocks for reading and writing. The queue accommodates address information, data, command information, byte enable information, decode information, and a tag. The tag is a 2 bit field used to identify the queued entries as address, last data, and burst data. In a preferred embodiment, single transactions are written to the queue with no wait states. In the case of an address entry, the address associated with the transaction is stored in the queue along with the command and decode information. A tag is also included that identifies the entry as an address. In the case of a final data entry, the data is stored in the next entry along with the byte enable information and a tag to indicate it is the last data of the transaction. In the case of a burst, the address entry is followed by multiple data entries that are each tagged as burst data. The final data entry of the burst will be tagged as the last data of the transaction in the same way as the data of a single transaction.
摘要翻译：公开了用于在图形控制器内的主机总线和内部系统总线之间传送数据的事务队列。队列包括具有用于读取和写入的独立时钟的先进先出（FIFO）存储器。队列容纳地址信息，数据，命令信息，字节使能信息，解码信息和标签。标签是用于将排队条目标识为地址，最后数据和突发数据的2位字段。在优选实施例中，单个事务被写入队列而没有等待状态。在地址条目的情况下，与事务相关联的地址与命令和解码信息一起存储在队列中。还包括将该条目标识为地址的标签。在最终数据输入的情况下，数据与字节使能信息一起存储在下一个条目中，并且标签表示它是事务的最后数据。在突发的情况下，地址条目后跟多个数据条目，每个条目被标记为突发数据。突发的最终数据输入将以与单个事务的数据相同的方式被标记为事务的最后数据。

6. 发明授权

US5754191A Method and apparatus for optimizing pixel data write operations to a tile based frame buffer 失效
标题翻译：将像素数据写入操作优化到基于瓦片的帧缓冲器的方法和装置
公开(公告)号：US5754191A
公开(公告)日：1998-05-19
申请号：US577988
申请日：1995-12-22
申请人： Karl Scott Mills , Jeffrey Michael Holmes , Mark Emil Bonnelycke , Richard Charles Andrew Owen
发明人： Karl Scott Mills , Jeffrey Michael Holmes , Mark Emil Bonnelycke , Richard Charles Andrew Owen
IPC分类号： G06F3/14 , G09G5/02 , G09G5/393 , G09G5/395 , G06F13/00
CPC分类号： G09G5/393 , G06F3/14 , G09G5/02 , G09G5/395 , G09G2340/12 , G09G2360/122
摘要： A method and apparatus for improving pixel data write operations to a tile-based frame buffer. The present invention includes a byte enable first-in first-out register for storing byte enable data for masking pixel data writes to a tile based frame buffer when the pixel data crosses a tile boundary. Pixel data generated by a graphics processor to the frame buffer may traverse multiple tiles. With each 64-bits of pixel data generated, a corresponding byte of byte enable data is generated as mask data for the frame buffer. The byte enable circuit of the present invention may be implemented as a circular shift register to allow the byte enable data to be shifted, rather than being "popped" after the pixel data has been written to the frame buffer. By shifting data rather than "popping" data, the byte enable circuit is able to retain portions of the byte enable data to enable a correct write of a pixel word which may traverse tile boundaries.
摘要翻译：一种用于将像素数据写入操作改进到基于瓦片的帧缓冲器的方法和装置。本发明包括一个字节使能先进先出寄存器，用于存储字节使能数据，用于当像素数据与图块边界交叉时，屏蔽对基于瓦片的帧缓冲器的像素数据写入。由图形处理器向帧缓冲器生成的像素数据可以遍历多个图块。在产生每个64位像素数据的情况下，生成字节使能数据的相应字节作为帧缓冲器的掩码数据。本发明的字节使能电路可以被实现为循环移位寄存器，以允许字节使能数据被移位，而不是在像素数据被写入到帧缓冲器之后被“弹出”。通过移位数据而不是“弹出”数据，字节使能电路能够保留字节使能数据的一部分，以使得能够正确地写入可能穿过块边界的像素字。

7. 发明授权

US5727139A Method and apparatus for minimizing number of pixel data fetches required for a stretch operation of video images 失效
标题翻译：用于最小化视频图像的拉伸操作所需的像素数据提取的方法和装置
公开(公告)号：US5727139A
公开(公告)日：1998-03-10
申请号：US536553
申请日：1995-09-29
申请人： Richard Charles Andrew Owen , Karl Scott Mills , Mark Emill Bonnelycke , Bradley Andrew May , Vernon Dennis Hasz
发明人： Richard Charles Andrew Owen , Karl Scott Mills , Mark Emill Bonnelycke , Bradley Andrew May , Vernon Dennis Hasz
IPC分类号： G06T3/40 , G06F15/00
CPC分类号： G06T3/4023
摘要： A method and apparatus to stretch video images in a graphics controller chip of a computer system. The graphics controller chip fetches four pixel data comprising two pixel data each from a first scan line and a second scan line of a source video image, and generates a set of additional pixels in a rectangular area defined by the four pixels. The graphics controller chip stores the pixels of rectangular portions in a display memory, and displays the pixel data of the stretched video image in a scan line order.
摘要翻译：一种用于在计算机系统的图形控制器芯片中拉伸视频图像的方法和装置。图形控制器芯片从源视频图像的第一扫描线和第二扫描线获取包括两个像素数据的四个像素数据，并且生成由四个像素限定的矩形区域中的一组附加像素。图形控制器芯片将矩形部分的像素存储在显示存储器中，并以扫描线顺序显示延伸的视频图像的像素数据。

8. 发明授权

US5959637A Method and apparatus for executing a raster operation in a graphics controller circuit 失效
标题翻译：用于在图形控制器电路中执行光栅操作的方法和装置
公开(公告)号：US5959637A
公开(公告)日：1999-09-28
申请号：US667248
申请日：1996-06-20
申请人： Karl Scott Mills , Jeffrey Michael Holmes , Mark Emil Bonnelycke , Richard Charles Andrew Owen
发明人： Karl Scott Mills , Jeffrey Michael Holmes , Mark Emil Bonnelycke , Richard Charles Andrew Owen
IPC分类号： G06F3/14 , G09G5/02 , G09G5/36 , G09G5/393 , G06T91/20 , G06F15/00
CPC分类号： G06F3/14 , G09G5/02 , G09G5/363 , G09G5/393 , G09G2340/12
摘要： A graphics controller circuit comprising a plurality of pipelines for performing a set of operations on a stream of input pixel data to generate at least a first operand and a second operand. A rasterop unit in the graphics controller circuit may receive the first operand and the second operand, and execute a raster operation using the first operand and the second operand to generate a set of display pixel data. The graphics controller circuit may further comprise a transparency unit for generating a write enable mask corresponding to the set of display pixel data. A display memory may selectively store or block the set of display pixel data according to the write enable mask. As the graphics controller generates display signals from the display data stored in display memory, a transparency operation may be performed.
摘要翻译：一种图形控制器电路，包括用于对输入像素数据流执行一组操作以产生至少第一操作数和第二操作数的多条流水线。图形控制器电路中的光栅单元可以接收第一操作数和第二操作数，并且使用第一操作数和第二操作数执行光栅操作以生成一组显示像素数据。图形控制器电路还可以包括透明度单元，用于产生与该组显示像素数据相对应的写使能掩码。显示存储器可以根据写使能掩模选择性地存储或阻挡该组显示像素数据。当图形控制器从存储在显示存储器中的显示数据产生显示信号时，可以执行透明度操作。

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