专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US08010856B2 Methods for analyzing scan chains, and for determining numbers or locations of hold time faults in scan chains 有权
标题翻译：分析扫描链以及确定扫描链中保持时间故障数量或位置的方法
公开(公告)号：US08010856B2
公开(公告)日：2011-08-30
申请号：US12058768
申请日：2008-03-31
申请人： Stephen A. Cannon , Richard C. Dokken , Alfred L. Crouch , Gary A. Winblad
发明人： Stephen A. Cannon , Richard C. Dokken , Alfred L. Crouch , Gary A. Winblad
IPC分类号： G01R31/28
CPC分类号： G01R31/318536
摘要： In a method for determining a number of possible hold time faults in a scan chain of a DUT, an environmental variable of the scan chain is set to a value believed to cause a hold time fault in the scan chain, and then a pattern is shifted through the scan chain. The pattern has a background pattern of at least n contiguous bits of a first logic state, followed by at least one bit of a second logic state, where n is a length of the scan chain. The number of possible hold time faults in the scan chain can be determined as a difference between i) a clock cycle when the at least one bit is expected to cause a transition at an output of the scan chain, and ii) a clock cycle when the at least one bit actually causes a transition at the output of the scan chain. If a value of the environmental variable at which the scan chain operates correctly can be determined, the location of one or more hold time faults can also be determined.
摘要翻译：在用于确定DUT的扫描链中可能的保持时间故障的数量的方法中，扫描链的环境变量被设置为被认为在扫描链中引起保持时间故障的值，然后模式被移位通过扫描链。该模式具有第一逻辑状态的至少n个连续位的后台模式，随后是第二逻辑状态的至少一位，其中n是扫描链的长度。扫描链中可能的保持时间故障的数量可以被确定为i）当预期至少一个位导致扫描链的输出处的转变时的时钟周期之间的差异，以及ii）时钟周期至少一个位实际上在扫描链的输出端引起转换。如果可以确定扫描链正确操作的环境变量的值，则也可以确定一个或多个保持时间故障的位置。

2. 发明授权

US08006149B2 System and method for device performance characterization in physical and logical domains with AC SCAN testing 有权
标题翻译：使用AC SCAN测试的物理和逻辑域中的器件性能表征的系统和方法
公开(公告)号：US08006149B2
公开(公告)日：2011-08-23
申请号：US11563612
申请日：2006-11-27
申请人： Richard C. Dokken , Gerald S. Chan , Phillip D. Burlison
发明人： Richard C. Dokken , Gerald S. Chan , Phillip D. Burlison
IPC分类号： G01R31/3177 , G01R31/40
CPC分类号： G01R31/318547 , G01R31/318569
摘要： A method for data logging from inside a semiconductor device, yielding timing performance information about the logic behind each and every flip-flop in the scan chain and displaying the sensitivity of certain flipflops to speed related manufacturing defects. The method comprises steps for testing, measuring, storing, and analyzing records for frequency characterization of complex digital semiconductors.
摘要翻译：一种用于从半导体器件内部进行数据记录的方法，产生关于扫描链中每个触发器后面的逻辑的定时性能信息，并且显示某些触发器对于加速相关制造缺陷的灵敏度。该方法包括用于测试，测量，存储和分析复数数字半导体频率表征记录的步骤。

3. 发明申请

US20090113263A1 METHODS FOR ANALYZING SCAN CHAINS, AND FOR DETERMINING NUMBERS OR LOCATIONS OF HOLD TIME FAULTS IN SCAN CHAINS 有权
标题翻译：用于分析扫描链的方法，以及用于确定扫描链中保持时间故障的数字或位置
公开(公告)号：US20090113263A1
公开(公告)日：2009-04-30
申请号：US12058768
申请日：2008-03-31
申请人： Stephen A. Cannon , Richard C. Dokken , Alfred L. Crouch , Gary A. Winblad
发明人： Stephen A. Cannon , Richard C. Dokken , Alfred L. Crouch , Gary A. Winblad
IPC分类号： G01R31/3177 , G06F11/25
CPC分类号： G01R31/318536
摘要： In a method for determining a number of possible hold time faults in a scan chain of a DUT, an environmental variable of the scan chain is set to a value believed to cause a hold time fault in the scan chain, and then a pattern is shifted through the scan chain. The pattern has a background pattern of at least n contiguous bits of a first logic state, followed by at least one bit of a second logic state, where n is a length of the scan chain. The number of possible hold time faults in the scan chain can be determined as a difference between i) a clock cycle when the at least one bit is expected to cause a transition at an output of the scan chain, and ii) a clock cycle when the at least one bit actually causes a transition at the output of the scan chain. If a value of the environmental variable at which the scan chain operates correctly can be determined, the location of one or more hold time faults can also be determined.
摘要翻译：在用于确定DUT的扫描链中可能的保持时间故障的数量的方法中，扫描链的环境变量被设置为被认为在扫描链中引起保持时间故障的值，然后模式被移位通过扫描链。该模式具有第一逻辑状态的至少n个连续位的后台模式，随后是第二逻辑状态的至少一位，其中n是扫描链的长度。扫描链中可能的保持时间故障的数量可以被确定为i）当预期至少一个位导致扫描链的输出处的转变时的时钟周期之间的差异，以及ii）时钟周期至少一个位实际上在扫描链的输出端引起转换。如果可以确定扫描链正确操作的环境变量的值，则也可以确定一个或多个保持时间故障的位置。

4. 发明申请

US20080104468A1 Process for improving design limited yield by efficiently capturing and storing production test data for analysis using checksums, hash values, or digital fault signatures 有权
标题翻译：通过有效地捕获和存储使用校验和，散列值或数字故障签名进行分析的生产测试数据来提高设计有限产量的过程
公开(公告)号：US20080104468A1
公开(公告)日：2008-05-01
申请号：US11565616
申请日：2006-11-30
申请人： GERALD S. CHAN , RICHARD C. DOKKEN
发明人： GERALD S. CHAN , RICHARD C. DOKKEN
IPC分类号： G01R31/28
CPC分类号： G01R31/318547 , G01R31/31703
摘要： A process for conserving storage space and time while recording not only a pass or fail result per die but also additional failure test pattern data by computing and comparing digital fault signatures or hash values on a tester.
摘要翻译：节省存储空间和时间的过程，不仅记录了每个芯片的通过或失败结果，还通过计算和比较测试仪上的数字故障签名或散列值，以及额外的故障测试模式数据。

5. 发明授权

US08615691B2 Process for improving design-limited yield by localizing potential faults from production test data 有权
标题翻译：通过将生产测试数据中的潜在故障进行定位来提高设计限制产量的过程
公开(公告)号：US08615691B2
公开(公告)日：2013-12-24
申请号：US11682314
申请日：2007-03-06
申请人： Richard C Dokken , Gerald S. Chan , John C Potter , Alfred L Crouch
发明人： Richard C Dokken , Gerald S. Chan , John C Potter , Alfred L Crouch
IPC分类号： G01R31/3177 , G01R31/40
CPC分类号： G01R31/318533
摘要： A process for improving design-limited yield by collecting test fail data, converting to electrical faults, and localizing to physical area on semiconductor die. The steps of identifying an area on a wafer containing a fault to enable the analysis of specific defects, accumulating data suitable for yield monitoring analysis based on pattern test failures logged on scan cells in scan chains on automatic test equipment, and translating scan cell and scan chain failure reports to geometric locations of electrical structures on wafers.
摘要翻译：通过收集测试失败数据，转换为电气故障并将其定位到半导体裸片上的物理区域来提高设计限制产量的过程。识别包含故障的晶片上的区域以使得能够分析特定缺陷的步骤，基于自动测试设备上的扫描链中记录在扫描单元上的模式测试故障累积适合于产量监测分析的数据，以及翻译扫描单元和扫描链条故障报告给晶圆上的电气结构的几何位置。

6. 发明授权

US08060851B2 Method for operating a secure semiconductor IP server to support failure analysis 有权
标题翻译：用于操作安全半导体IP服务器以支持故障分析的方法
公开(公告)号：US08060851B2
公开(公告)日：2011-11-15
申请号：US11850342
申请日：2007-09-05
申请人： Richard C. Dokken , Gerald S. Chan , Jacob J Orbon , Alfred L Crouch
发明人： Richard C. Dokken , Gerald S. Chan , Jacob J Orbon , Alfred L Crouch
IPC分类号： G06F17/50
CPC分类号： G01R31/318541 , G01R31/318552
摘要： A method for operating a secure semiconductor IP access server to support failure analysis. A client presents a test failure and failure type to an automated server which traverses an electronic product design, definition, and test database to report specifically those components and interconnect likely to cause the failure with geometrical information which may be displayed on the client. Other aspects of semiconductor IP are protected by the server by limiting the trace mechanism and renaming components.
摘要翻译：一种用于操作安全半导体IP访问服务器以支持故障分析的方法。客户端向自动化服务器呈现测试失败和故障类型，该服务器遍历电子产品设计，定义和测试数据库，以具体报告那些组件和互连可能导致故障与可能在客户端上显示的几何信息。半导体IP的其他方面由服务器通过限制跟踪机制和重命名组件来保护。

7. 发明申请

US20090113265A1 LOCATING HOLD TIME VIOLATIONS IN SCAN CHAINS BY GENERATING PATTERNS ON ATE 有权
标题翻译：通过生成模式来定位扫描链中的时间违反
公开(公告)号：US20090113265A1
公开(公告)日：2009-04-30
申请号：US11931847
申请日：2007-10-31
申请人： Stephen A. Cannon , Richard C. Dokken , Alfred L. Crouch , Gary A. Winblad
发明人： Stephen A. Cannon , Richard C. Dokken , Alfred L. Crouch , Gary A. Winblad
IPC分类号： G01R31/28
CPC分类号： G01R31/318544 , G01R31/318525 , G01R35/00
摘要： A method for determining that failures in semiconductor test are due to a defect potentially causing a hold time violation in a scan cell in a scan chain, counting the number of potential defects, and, if possible, localizing, and ameliorating hold time defects in a scan chain.
摘要翻译：用于确定半导体测试中的故障的方法是由于潜在地导致扫描链中的扫描单元中的保持时间违规的缺陷，计数潜在缺陷的数量，以及如果可能的话，定位和改善保持时间缺陷扫描链。

8. 发明申请

US20080126896A1 System and Method for Device Performance Characterization in Physical and Logical Domains with AC SCAN Testing 有权
标题翻译：使用AC SCAN测试的物理和逻辑域中的器件性能表征的系统和方法
公开(公告)号：US20080126896A1
公开(公告)日：2008-05-29
申请号：US11563612
申请日：2006-11-27
申请人： Richard C. Dokken , Gerald S. Chan , Phillip D. Burlison
发明人： Richard C. Dokken , Gerald S. Chan , Phillip D. Burlison
IPC分类号： G01R31/28
CPC分类号： G01R31/318547 , G01R31/318569
摘要： A method for data logging from inside a semiconductor device, yielding timing performance information about the logic behind each and every flip-flop in the scan chain and displaying the sensitivity of certain flipflops to speed related manufacturing defects. The method comprises steps for testing, measuring, storing, and analyzing records for frequency characterization of complex digital semiconductors.
摘要翻译：一种用于从半导体器件内部进行数据记录的方法，产生关于扫描链中每个触发器后面的逻辑的定时性能信息，并且显示某些触发器对于加速相关制造缺陷的灵敏度。该方法包括用于测试，测量，存储和分析复数数字半导体频率表征记录的步骤。

9. 发明申请

US20080091981A1 PROCESS FOR IMPROVING DESIGN-LIMITED YIELD BY LOCALIZING POTENTIAL FAULTS FROM PRODUCTION TEST DATA 有权
标题翻译：通过从生产测试数据中定位潜在缺陷来改进设计有限公司的过程
公开(公告)号：US20080091981A1
公开(公告)日：2008-04-17
申请号：US11682314
申请日：2007-03-06
申请人： RICHARD C. DOKKEN , Gerald S. Chan , John C. Potter , Alfred L. Crouch
发明人： RICHARD C. DOKKEN , Gerald S. Chan , John C. Potter , Alfred L. Crouch
IPC分类号： G06F11/00
CPC分类号： G01R31/318533
摘要： A process for improving design-limited yield by collecting test fail data, converting to electrical faults, and localizing to physical area on semiconductor die. The steps of identifying an area on a wafer containing a fault to enable the analysis of specific defects, accumulating data suitable for yield monitoring analysis based on pattern test failures logged on scan cells in scan chains on automatic test equipment, and translating scan cell and scan chain failure reports to geometric locations of electrical structures on wafers.
摘要翻译：通过收集测试失败数据，转换为电气故障并将其定位到半导体裸片上的物理区域来提高设计限制产量的过程。识别包含故障的晶片上的区域以使得能够分析特定缺陷的步骤，基于自动测试设备上的扫描链中记录在扫描单元上的模式测试故障累积适合于产量监测分析的数据，以及翻译扫描单元和扫描链条故障报告给晶圆上的电气结构的几何位置。

10. 发明授权

US07047463B1 Method and system for automatically determining a testing order when executing a test flow 有权
标题翻译：执行测试流程时自动确定测试顺序的方法和系统
公开(公告)号：US07047463B1
公开(公告)日：2006-05-16
申请号：US10642000
申请日：2003-08-15
申请人： Donald V. Organ , Richard C. Dokken
发明人： Donald V. Organ , Richard C. Dokken
IPC分类号： G01R31/28
CPC分类号： G01R31/2893 , G01R31/2834
摘要： A method and system for automated multisite testing. Specifically, in one embodiment, a method is disclosed for determining a testing order of plurality of testing operations of a test flow in a multisite testing environment. The method begins by automatically walking through the test flow by performing recursion on the plurality of testing operations. Next, the method automatically assigns a plurality of relative priorities to the plurality of testing operations. The plurality of relative priorities determine the testing order used when executing each of the plurality of testing operations in said test flow. Each of the plurality of testing operations is executed only once when testing a plurality of devices under test (DUTs) in the multisite testing environment.
摘要翻译：一种用于自动多站点测试的方法和系统。具体地，在一个实施例中，公开了一种用于确定多站点测试环境中的测试流的多个测试操作的测试顺序的方法。该方法通过在多个测试操作上执行递归来自动走过测试流程。接下来，该方法自动地将多个相对优先级分配给多个测试操作。多个相对优先级确定在执行所述测试流程中的多个测试操作中的每一个时使用的测试顺序。当在多站点测试环境中测试多个待测设备（DUT）时，多个测试操作中的每一个仅执行一次。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式