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1. 发明申请

US20110241085A1 DUAL SIDEWALL SPACER FOR SEAM PROTECTION OF A PATTERNED STRUCTURE 有权
标题翻译：用于保护图案结构的双面隔板
公开(公告)号：US20110241085A1
公开(公告)日：2011-10-06
申请号：US12751891
申请日：2010-03-31
申请人： David L. O'Meara , Anthony Dip , Aelan Mosden , Pao-Hwa Chou , Richard A. Conti
发明人： David L. O'Meara , Anthony Dip , Aelan Mosden , Pao-Hwa Chou , Richard A. Conti
IPC分类号： H01L29/78 , H01L21/311
CPC分类号： H01L29/4983 , H01L29/665 , H01L29/6656 , H01L29/6659 , H01L29/7833
摘要： A semiconducting device with a dual sidewall spacer and method of forming are provided. The method includes: depositing a first spacer layer over a patterned structure, the first spacer layer having a seam propagating through a thickness of the first spacer layer near an interface region of a surface of the substrate and a sidewall of the patterned structure, etching the first spacer layer to form a residual spacer at the interface region, where the residual spacer coats less than the entirety of the sidewall of the patterned structure, depositing a second spacer layer on the residual spacer and on the sidewall of the patterned structure not coated by the residual spacer, the second spacer layer being seam-free on the seam of the residual spacer, and etching the second spacer layer to form a second spacer coating the residual spacer and coating the sidewall of the patterned structure not coated by the residual spacer.
摘要翻译：提供了具有双侧壁间隔件和成形方法的半导体器件。该方法包括：在图案化结构上沉积第一间隔层，第一间隔层具有在衬底的表面的界面区附近传播穿过第一间隔层的厚度的接缝和图案化结构的侧壁，蚀刻第一间隔层，以在界面区域处形成残留间隔物，其中残余间隔物涂覆小于图案化结构的侧壁的整体，在剩余间隔物上和在图案化结构的侧壁上沉积第二间隔层，所述剩余间隔物，所述第二间隔层在所述残余间隔物的接缝上是无缝的，并且蚀刻所述第二间隔层以形成涂覆所述剩余间隔物并涂覆未被所述残留间隔物涂覆的所述图案化结构的侧壁的第二间隔物。

2. 发明申请

US20090243031A1 STRUCTURE AND METHOD TO CONTROL OXIDATION IN HIGH-K GATE STRUCTURES 有权
标题翻译：控制高K门结构氧化的结构和方法
公开(公告)号：US20090243031A1
公开(公告)日：2009-10-01
申请号：US12055682
申请日：2008-03-26
申请人： Wesley C. Natzle , Renee T. Mo , Rashmi Jha , Kathryn T. Schonenberg , Richard A. Conti
发明人： Wesley C. Natzle , Renee T. Mo , Rashmi Jha , Kathryn T. Schonenberg , Richard A. Conti
IPC分类号： H01L29/49 , H01L21/441
CPC分类号： H01L21/76224 , H01L21/28123 , H01L29/517
摘要： In one embodiment, the present invention provides a method of fabricating a semiconducting device that includes providing a substrate including at least one semiconducting region and at least one oxygen source region; forming an oxygen barrier material atop portions of an upper surface of the at least one oxygen region; forming a high-k gate dielectric on the substrate including the at least one semiconducting region, wherein oxygen barrier material separates the high-k gate dielectric from the at least one oxygen source material; and forming a gate conductor atop the high-k gate dielectric.
摘要翻译：在一个实施例中，本发明提供一种制造半导体器件的方法，其包括提供包括至少一个半导体区域和至少一个氧源区域的衬底; 在所述至少一个氧区的上表面的部分顶部形成氧阻隔材料; 在包括所述至少一个半导体区域的衬底上形成高k栅极电介质，其中氧阻挡材料将所述高k栅极电介质与所述至少一个氧源材料分离; 并在高k栅极电介质的顶部形成栅极导体。

3. 发明授权

US07485573B2 Process of making a semiconductor device using multiple antireflective materials 失效
标题翻译：制造使用多种抗反射材料的半导体器件的工艺
公开(公告)号：US07485573B2
公开(公告)日：2009-02-03
申请号：US11356027
申请日：2006-02-17
申请人： Marie Angelopoulos , Katherina E. Babich , Sean D. Burns , Richard A. Conti , Allen H. Gabor , Scott D. Halle , Arpan P. Mahorowala , Dirk Pfeiffer
发明人： Marie Angelopoulos , Katherina E. Babich , Sean D. Burns , Richard A. Conti , Allen H. Gabor , Scott D. Halle , Arpan P. Mahorowala , Dirk Pfeiffer
IPC分类号： H01L21/4763
CPC分类号： G03F7/091 , Y10S438/952
摘要： A lithographic structure consisting essentially of: an organic antireflective material disposed on a substrate; a vapor-deposited RCHX material, wherein R is one or more elements selected from the group consisting of Si, Ge, B, Sn, Fe and Ti, and wherein X is not present or is one or more elements selected from the group consisting of O, N, S and F; and a photoresist material disposed on the RCHX material. The invention is also directed to methods of making the lithographic structure, and using the structure to pattern a substrate.
摘要翻译：一种光刻结构，主要由以下部分组成：设置在基板上的有机抗反射材料; 气相沉积的RCHX材料，其中R是选自Si，Ge，B，Sn，Fe和Ti中的一种或多种元素，并且其中X不存在或者是选自以下的一种或多种元素： O，N，S和F; 以及设置在RCHX材料上的光致抗蚀剂材料。本发明还涉及制造光刻结构的方法，并且使用该结构来图案化衬底。

4. 发明授权

US07084079B2 Method for low temperature chemical vapor deposition of low-k films using selected cyclosiloxane and ozone gases for semiconductor applications 失效
公开(公告)号：US07084079B2
公开(公告)日：2006-08-01
申请号：US10299357
申请日：2002-11-18
申请人： Richard A. Conti , Daniel C. Edelstein , Gill Yong Lee
发明人： Richard A. Conti , Daniel C. Edelstein , Gill Yong Lee
IPC分类号： H01L21/469
CPC分类号： H01L21/02271 , C23C16/401 , H01L21/02112 , H01L21/02129 , H01L21/02205 , H01L21/02216 , H01L21/3122 , H01L21/31604 , H01L21/31625 , H01L21/31629 , H01L21/31633 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： A method is described for forming a low-k dielectric film, in particular, a pre-metal dielectric (PMD) on a semiconductor wafer which has good gap-filling characteristics. The method uses a thermal sub-atmospheric CVD process that includes a carbon-containing organometallic precusor such as TMCTS or OMCTS, an ozone-containing gas, and a source of dopants for gettering alkali elements and for lowering the reflow temperature of the dielectric while attaining the desired low-k and gap-filling properties of the dielectric film. Phosphorous is a preferred dopant for gettering alkali elements such as sodium. Additional dopants for lowering the reflow temperature include, but are not limited to boron, germanium, arsenic, fluorine or combinations thereof.

5. 发明授权

US06740539B2 Carbon-graded layer for improved adhesion of low-k dielectrics to silicon substrates 有权
标题翻译：碳分级层，用于改善低k电介质与硅衬底的粘附性
公开(公告)号：US06740539B2
公开(公告)日：2004-05-25
申请号：US10366149
申请日：2003-02-13
申请人： Richard A. Conti , Prakash Chimanlal Dev , David M. Dobuzinsky , Daniel C. Edelstein , Gill Y. Lee , Kia-Seng Low , Padraic C. Shafer , Alexander Simpson , Peter Wrschka
发明人： Richard A. Conti , Prakash Chimanlal Dev , David M. Dobuzinsky , Daniel C. Edelstein , Gill Y. Lee , Kia-Seng Low , Padraic C. Shafer , Alexander Simpson , Peter Wrschka
IPC分类号： H01L5140
CPC分类号： H01L21/28185 , H01L21/02126 , H01L21/02274 , H01L21/28194 , H01L21/31633 , H01L23/5329 , H01L23/53295 , H01L29/513 , H01L29/517 , H01L29/518 , H01L2924/0002 , H01L2924/00
摘要： A structure and method for an insulator layer having carbon-graded layers above a substrate is disclosed, wherein the concentration of carbon increases in each successive carbon-graded layer above the substrate. The insulator comprises a low-k dielectric having a dielectric constant less than 3.3. The carbon-graded layer increases adhesion between the substrate and the insulator and between the insulator and the conductor layer. The structure may also include stabilization interfaces between the carbon-graded layers. More specifically, the carbon-graded layers include a first layer adjacent the substrate having a carbon content between about 5% and 20%, a second layer above the first layer having a carbon content between about 10% and 30%, and a third layer above the second layer having a carbon content between about 20% and 40%.
摘要翻译：公开了一种在衬底上方具有碳分级层的绝缘体层的结构和方法，其中在衬底上方的每个连续的碳分级层中碳的浓度增加。绝缘体包括介电常数小于3.3的低k电介质。碳分级层增加了衬底和绝缘体之间以及绝缘体和导体层之间的粘合性。该结构还可以包括碳分级层之间的稳定界面。更具体地，碳分级层包括邻近基底的第一层，其碳含量在约5％至20％之间，第一层上方的碳含量在约10％至30％之间，第三层在第二层上方具有约20％至40％的碳含量。

6. 发明授权

US06500772B2 Methods and materials for depositing films on semiconductor substrates 失效
标题翻译：用于在半导体衬底上沉积膜的方法和材料
公开(公告)号：US06500772B2
公开(公告)日：2002-12-31
申请号：US09757072
申请日：2001-01-08
申请人： Ashima B. Chakravarti , Richard A. Conti , Chester Dziobkowski , Thomas Ivers , Paul Jamison , Frank Liucci
发明人： Ashima B. Chakravarti , Richard A. Conti , Chester Dziobkowski , Thomas Ivers , Paul Jamison , Frank Liucci
IPC分类号： H01L2131
CPC分类号： H01L21/02126 , C23C16/30 , H01L21/02167 , H01L21/02222 , H01L21/02274 , H01L21/0332 , H01L21/3145 , H01L21/31608 , H01L21/3185
摘要： A method of depositing a film on a substrate, comprising placing the substrate in the presence of plasma energy, and contacting the substrate with a reactive gas component comprising a compound of the formula (R—NH)4−nSiXn, wherein R is an alkyl group, n is 1, 2, or 3, and X is selected from hydrogen or the halogens. The reactive gas composition may further comprise an oxidizer and/or a reducing agent.
摘要翻译：一种在衬底上沉积膜的方法，包括在存在等离子体能量的情况下放置衬底，并使衬底与包含式（R-NH）4-nSiXn的化合物的反应性气体组分接触，其中R是烷基基团，n为1,2或3，并且X选自氢或卤素。反应性气体组合物还可以包含氧化剂和/或还原剂。

7. 发明授权

US06486015B1 Low temperature carbon rich oxy-nitride for improved RIE selectivity 失效
标题翻译：低温富碳氧氮化物，提高RIE选择性
公开(公告)号：US06486015B1
公开(公告)日：2002-11-26
申请号：US09557363
申请日：2000-04-25
申请人： Nirmal Chaudhary , Richard A. Conti
发明人： Nirmal Chaudhary , Richard A. Conti
IPC分类号： H01L218238
CPC分类号： H01L21/02271 , H01L21/02126 , H01L21/02222 , H01L21/31116 , H01L21/76834 , H01L21/76897 , H01L27/10855 , H01L27/10888
摘要： Reactive ion etch (RIE) selectivity during etching of a feature nearby embedded structure is improved by using a silicon oxynitride layer formed with carbonization throughout layer.
摘要翻译：通过使用在整个层上形成碳氧化的氮氧化硅层来改善蚀刻邻近嵌入结构的特征期间的反应离子蚀刻（RIE）选择性。

8. 发明授权

US06274440B1 Manufacturing of cavity fuses on gate conductor level 失效
标题翻译：在栅极导体级制造腔体保险丝
公开(公告)号：US06274440B1
公开(公告)日：2001-08-14
申请号：US09282134
申请日：1999-03-31
申请人： Kenneth C. Arndt , Axel C. Brintzinger , Richard A. Conti , Donna R. Cote , Chandrasekhar Narayan , Ravikumar Ramachandran , Thomas S. Rupp , Senthil K. Srinivasan
发明人： Kenneth C. Arndt , Axel C. Brintzinger , Richard A. Conti , Donna R. Cote , Chandrasekhar Narayan , Ravikumar Ramachandran , Thomas S. Rupp , Senthil K. Srinivasan
IPC分类号： H01L21336
CPC分类号： H01L23/5258 , H01L23/5256 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： A structure and method for making a cavity fuse over a gate conductor stack. The method includes providing a semiconductor substrate having a gate conductor stack over a shallow trench isolation region, forming oxide layers on the substrate about the gate conductor stack, etching electrical contact holes through the oxide layers to the substrate, filling the electrical contact holes with a first conductive material to establish electrical contact with the gate conductor stack, etching a pattern in an uppermost oxide layer of the oxide layers, depositing a conductive layer of a second conductive material over the oxide layers and the electrical contacts, planarizing the conductive layer whereby the conductive material remains only in the pattern, anisotropically etching the oxide layers to form at least one etching hole through the oxide layers to the shallow trench isolation region, and isotropically etching at least a portion of the oxide layers about the etching hole, whereby a cavity is formed beneath at least a portion of the conductive layer pattern, the gate conductor stack comprising a fuse.
摘要翻译：用于在栅极导体堆叠上形成腔体熔断器的结构和方法。该方法包括提供在浅沟槽隔离区域上具有栅极导体堆叠的半导体衬底，在栅极导体堆叠周围形成衬底周围的氧化物层，蚀刻通过氧化物层到衬底的电接触孔，第一导电材料以与栅极导体堆叠建立电接触，蚀刻氧化物层的最上面的氧化物层中的图案，在氧化物层和电触点上沉积第二导电材料的导电层，平坦化导电层，由此导电材料仅保留在图案中，各向异性地蚀刻氧化物层以形成通过氧化物层到浅沟槽隔离区域的至少一个蚀刻孔，并且在蚀刻孔周围各向同性蚀刻至少一部分氧化层，形成在导电层图案的至少一部分之下，g 包括保险丝的导体堆叠。

9. 发明授权

US06232222B1 Method of eliminating a critical mask using a blockout mask and a resulting semiconductor structure 失效
标题翻译：使用阻挡掩模和所得半导体结构消除临界掩模的方法
公开(公告)号：US06232222B1
公开(公告)日：2001-05-15
申请号：US09395418
申请日：1999-09-14
申请人： Michael Armacost , Richard A. Conti , Jeffrey P. Gambino , Jeremy K. Stephens
发明人： Michael Armacost , Richard A. Conti , Jeffrey P. Gambino , Jeremy K. Stephens
IPC分类号： H01L214763
CPC分类号： H01L21/76897 , H01L21/31144 , H01L27/10873 , H01L27/10894
摘要： A method of forming a semiconductor structure may include forming a semiconductor substrate having an array region and a support region, forming a semiconductor substrate and a gate stack over the support region of the substrate and applying a critical mask over the support region and the array region. The critical mask may have a first opening at an area corresponding to the array region and a second opening at an area corresponding to the support region. Contact holes may be formed in a glass layer at areas corresponding to the first and second opening. After removing the critical mask, a first blockout mask may be applied over the array region and a first conductive type dopant may be added to exposed polysilicon corresponding to openings of the blockout mask or gate contacts may be formed.
摘要翻译：形成半导体结构的方法可以包括形成具有阵列区域和支撑区域的半导体衬底，在衬底的支撑区域上形成半导体衬底和栅叠层，并在衬底区域和阵列区域上施加临界掩模。临界掩模可以在对应于阵列区域的区域处具有第一开口，并且在对应于支撑区域的区域处具有第二开口。可以在对应于第一和第二开口的区域的玻璃层中形成接触孔。在去除临界掩模之后，可以在阵列区域上施加第一堵塞掩模，并且可以形成第一导电型掺杂剂，以对应于封闭掩模的开口或栅极触点形成对应于暴露的多晶硅。

10. 发明授权

US5939335A Method for reducing stress in the metallization of an integrated circuit 失效
标题翻译：降低集成电路金属化应力的方法
公开(公告)号：US5939335A
公开(公告)日：1999-08-17
申请号：US3107
申请日：1998-01-06
申请人： Kenneth C. Arndt , Richard A. Conti , David M. Dobuzinsky , Laertis Economikos , Jeffrey P. Gambino , Peter D. Hoh , Chandrasekhar Narayan
发明人： Kenneth C. Arndt , Richard A. Conti , David M. Dobuzinsky , Laertis Economikos , Jeffrey P. Gambino , Peter D. Hoh , Chandrasekhar Narayan
IPC分类号： H01L21/302 , H01L21/3065 , H01L21/3205 , H01L21/3213 , H01L21/768 , H01L21/336
CPC分类号： H01L21/76804 , H01L21/32136 , H01L21/76835 , H01L21/76885
摘要： The stresses commonly induced in the dielectrics of integrated circuits manufactured using metal patterning methods, such as reactive ion etching (RIE) and damascene techniques, can be reduced by rounding the lower corners associated with the features which are formed as part of the integrated circuit (e.g., the interconnects) before applying the outer (i.e., passivation) layer. In connection with the formation of metal lines patterned by a metal RIE process, such corner rounding can be achieved using a two-step metal etching process including a first step which produces a vertical sidewall and a second step which tapers lower portions of the vertical sidewall or which produces a tapered spacer along the lower portions of the vertical sidewall. This results in a rounded bottom corner which improves the step coverage of the overlying dielectric, in turn eliminating the potential for cracks. For metal lines patterned by damascene, such corner rounding can be achieved using a two-step trench etching process including a first step which produces a vertical sidewall, and a second step which produces a tapered sidewall along lower portions of the vertical sidewall.
摘要翻译：通过使与金属图案化方法（例如反应离子蚀刻（RIE）和镶嵌技术）一起制造的集成电路的电介质中通常感应的应力可以通过将与形成为集成电路的一部分的特征相关联的下角在施加外部（即钝化）层之前，例如，互连）。关于通过金属RIE工艺形成的金属线的形成，可以使用包括产生垂直侧壁的第一步骤和使垂直侧壁的下部逐渐变细的第二步骤的两步金属蚀刻工艺来实现这种角圆化或者沿着垂直侧壁的下部产生锥形间隔物。这导致圆角的底角，其改善了上覆电介质的台阶覆盖，从而消除了裂纹的可能性。对于由大马士革图案化的金属线，可以使用包括产生垂直侧壁的第一步骤的两步沟槽蚀刻工艺，以及沿着垂直侧壁的下部产生锥形侧壁的第二步骤来实现这种角落圆化。

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