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1. 发明授权

US4975908A Basic pulse frame and method for a digital signal multiplex hierarchy 失效
标题翻译：基本脉冲帧和数字信号复用层次的方法
公开(公告)号：US4975908A
公开(公告)日：1990-12-04
申请号：US281287
申请日：1988-12-08
申请人： Reginhard Pospischil
发明人： Reginhard Pospischil
IPC分类号： H04L5/22 , H04J3/00 , H04J3/16
CPC分类号： H04J3/1611
摘要： A basic pulse frame is disclosed that is employable in a synchronous network for digital signals of both the CEPT hierarchy as well as of the US hierarchy while maintaining maximum transmission capacity. The synchronous payload envelope (SPE) of the basic pulse frame is composed of 9 rows (Z) and 264 columns (Sp). A configuration that is optimum for signals of the CEPT hierarchy and a configuration that is optimum for signals of the US hierarchy is achieved, each of which also allow a transmission of sufficient signals of the other type. The configuration for preferably CEPT signals comprises 16 main blocks (HB1a-HB16a) and two auxiliary blocks (ZB1a, ZB2a). Both serve for the optional occupation with auxiliary signals; the second auxiliary block (ZB2a) also additionally serves for optional occupation with useful data signals. 204 bit/kbit/s CEPT signals transmitted in the synchronous payload envelope (SPE1a) can be completely inserted into 34,368 kbit/s signals of the higher CEPT hierarchy level [and] 1544 kbit/s US signals transmitted in the synchronous payload envelope (SPE1a) can be inserted with minimal loss of transmission capacity into 34,368 kbit/s signals of the higher CEPT hierarchy level that can follow a common 139,264 kbit/s hierarchy level. The configuration for preferably US signals contains 21 main blocks and 3 or 4 auxiliary blocks. The basic pulse frame is suitable for a world-wide digital signal multiplex hierarchy for a synchronous network.
摘要翻译：公开了一种基本脉冲帧，其可以在同步网络中用于CEPT层级以及US层次结构的数字信号，同时保持最大传输容量。基本脉冲帧的同步有效负载包络（SPE）由9行（Z）和264列（Sp）组成。实现了对于CEPT层级的信号和对于US层次的信号最佳的配置的配置，其中每一个还允许传输另一类型的足够的信号。优选CEPT信号的配置包括16个主块（HB1a-HB16a）和两个辅助块（ZB1a，ZB2a）。两者都用于辅助信号的可选占用; 第二辅助块（ZB2a）还用于有用数据信号的可选占用。在同步有效负载包络（SPE1a）中发送的204位/ kbit / s CEPT信号可以完全插入到同步有效载荷包络（SPE1a）中传输的较高CEPT层级[和] 1544 kbit / s US信号的34,368 kbit / s信号）可以以最小的传输容量损失插入到更高CEPT层级级别的34,368 kbit / s信号中，该信号可以遵循通用的139,264 kbit / s层级。优选US信号的配置包含21个主块和3个或4个辅助块。基本脉冲帧适用于同步网络的全球数字信号复用层次结构。

2. 发明授权

US4562422A CMI Decoder 失效
标题翻译： CMI解码器
公开(公告)号：US4562422A
公开(公告)日：1985-12-31
申请号：US571003
申请日：1984-01-16
申请人： Reginhard Pospischil
发明人： Reginhard Pospischil
IPC分类号： H03M5/04 , H04L25/49 , H03M5/12
CPC分类号： H04L25/4912
摘要： The invention involves a decoder for converting CMI-coded signals into binary signals. Existing decoders of this type have a comparatively elaborate design and high power consumption. The invention teaches an improved decoder which has an AND gate and a NOR gate with at least two inputs each, where one input of the two gates is connected directly to the signal input, and the other input is connected via a delay element with a delay corresponding to one half of a bit period of the CMI-coded signals. Each of the outputs of the two gates are connected separately to the inputs of an OR gate with the binary signals being available at its output further features of the present embodiment are a clock pulse generator and a CMI code protocol violation monitor. The present decoder can be used for transmission devices for of digital signals with bit rates of approximately 140 Mbit/sec.
摘要翻译：本发明涉及一种用于将CMI编码的信号转换成二进制信号的解码器。现有的这种解码器具有比较精细的设计和高功耗。本发明教导了一种改进的解码器，其具有与门和NOR门，每个具有至少两个输入，其中两个门的一个输入端直接连接到信号输入端，另一个输入端通过延迟元件连接对应于CMI编码信号的一个比特周期的一半。两个门的每个输出分别连接到OR门的输入，二进制信号在其输出端可用，本实施例的另外的特征是时钟脉冲发生器和CMI代码协议违规监视器。本解码器可用于具有大约140Mbit /秒的比特率的用于数字信号的传输设备。

3. 发明授权

US5267239A Cross-connect method for STM-1 signals of the synchronous digital multiplex hierarchy 失效
标题翻译：同步数字多路复用层次的STM-1信号的交叉连接方法
公开(公告)号：US5267239A
公开(公告)日：1993-11-30
申请号：US759729
申请日：1991-09-12
申请人： Reginhard Pospischil , Horst Mueller
发明人： Reginhard Pospischil , Horst Mueller
IPC分类号： H04J3/08 , H04J3/16 , H04Q11/04 , H04J3/12 , H04J3/22
CPC分类号： H04J3/1611 , H04J3/08 , H04J2203/0041
摘要： Cross-connect method for STM-1 signals of a synchronous digital multiplex hierarchy. Data blocks having differing multiplex structure of the synchronous digital multiplex hierarchy are processed in common in a cross-connect equipment. Controlled via a bus by a microprocessor, Au-4 administration units of STM-1 signals are resolved into virtual container groups of approximately the same length such as TUG-31 and TU-31. After the removal of auxiliary signals that are no longer required, an individual switching matrix network clock matching pointer and an individual switching matrix network overhead are respectively attached to these virtual container groups for the formation of uniform switching matrix network input signals (D39, D52). After a rearrangement in a switching matrix network, switching matrix network clock matching pointers and overheads are again taken from the switching matrix network output signals and are evaluated. Subsequently, the input signals (D39, D52) are subjected to a corresponding multiplexing method for the formation of new STM-1 signals. This method is employable in cross-connect and drop insert multiplexing equipment.
摘要翻译：用于同步数字多路复用层次结构的STM-1信号的交叉连接方法。在交叉连接设备中共同处理具有同步数字多路复用层级的不同复用结构的数据块。通过微处理器通过总线控制，STM-1信号的Au-4管理单元被分解成大致相同长度的虚拟容器组，例如TUG-31和TU-31。在删除不再需要的辅助信号之后，分别将各个交换矩阵网络时钟匹配指针和单独的交换矩阵网络开销附加到这些虚拟容器组，以形成均匀的交换矩阵网络输入信号（D39，D52）。在交换矩阵网络中进行重新排列后，从交换矩阵网络输出信号中再次获取开关矩阵网络时钟匹配指针和开销，并进行评估。随后，对输入信号（D39，D52）进行相应的多路复用方式，形成新的STM-1信号。该方法可用于交叉连接和插入复用设备。

4. 发明授权

US4406919A Method and apparatus for monitoring intermediate regenerative repeaters 失效
标题翻译：用于监控中间再生中继器的方法和装置
公开(公告)号：US4406919A
公开(公告)日：1983-09-27
申请号：US281849
申请日：1981-07-09
申请人： Reginhard Pospischil
发明人： Reginhard Pospischil
IPC分类号： H04B17/40 , H04L25/02 , H04L1/00
CPC分类号： H04B17/408 , H04B17/40
摘要： A method and apparatus for monitoring remotely-fed intermediate regenerative repeaters, in which each intermediate regenerative repeater contains a digital signal regenerative repeater for the digital data signal transmitted and a telemetry signal regenerative repeater for the generation and transmission of a telemetry signal, and in which the telemetry and digital data signals are transmitted over the same transmission line in different frequency bands, provides that the telemetry signal comprises various data blocks. Start and end are characterized by at least one start block and by two end blocks. The result of monitoring is transmitted in an error block. Moreover, a self-check during the transmission of the error block is conducted. The result of the self-check is subsequently transmitted in a test block. Each intermediate regenerative repeater further transmits the received telemetry signal unaltered and following the recognition of the last telemetry signal transmitted by the preceding intermediate regenerative repeater, the regenerative repeater transmits its own locally-generated telemetry signal. At the receiving end, there is an assignment of intermediate regenerative repeaters and telemetry signals so that faulty equipment may be determined by counting of the telemetry signals.
摘要翻译：一种用于监测远程馈给的中间再生中继器的方法和装置，其中每个中间再生中继器包含用于发送的数字数据信号的数字信号再生中继器和用于生成和传输遥测信号的遥测信号再生中继器，其中遥测和数字数据信号通过不同频带的相同传输线传输，提供遥测信号包括各种数据块。开始和结束由至少一个起始块和两个结束块表征。监视的结果在错误块中传输。此外，进行在发送错误块期间的自检。随后在测试块中发送自检的结果。每个中继再生中继器进一步发送接收到的遥测信号，并且在由先前的中间再生中继器发送的最后一个遥测信号的识别之后，再生中继器发送其本地的本地产生的遥测信号。在接收端，存在中间再生中继器和遥测信号的分配，从而可以通过计数遥测信号来确定故障设备。

5. 发明授权

US4744104A Self-synchronizing scrambler 失效
标题翻译：自同步扰频器
公开(公告)号：US4744104A
公开(公告)日：1988-05-10
申请号：US739700
申请日：1985-05-31
申请人： Reginhard Pospischil
发明人： Reginhard Pospischil
IPC分类号： H03M5/00 , H04L7/00 , H04L9/06 , H04L9/12 , H04L9/14 , H04L9/22 , H04L25/03 , H04L25/48 , H04L25/49 , H04L9/00
CPC分类号： H04L25/03872
摘要： A self-synchronizing scrambler for high bit rates has a number of scrambler stages supplied in parallel with bits of a signal to be scrambled, each scrambler stage having a series-connected pair of modulo-2 adders, and at least one shift register. A selected number of scrambler stages in the scrambler may include an additional shift register depending upon the number p of parallel bits in the signal to be scrambled, and the total number n of shift registers in the scrambler. The number of scrambler stages having two shift registers is n-p and the number of following scrambler stages having one shift register is 2 p-n. For suppressing short periods, a further modulo-2 adder can be connected between the original two modulo-2 adders, the additional modulo-2 adder inverting at least one bit of the signal for the short periods.
摘要翻译：用于高比特率的自同步扰频器具有与要加扰的信号的比特并行提供的多个扰频器级，每个扰频器级具有串联连接的模2加法器和至少一个移位寄存器。加扰器中选定数量的加扰器级可以包括附加移位寄存器，这取决于要加扰的信号中并行比特的数目p和加扰器中的移位寄存器的总数n。具有两个移位寄存器的扰频器级数为n-p，并且具有一个移位寄存器的后续扰频器级数为2p-n。为了抑制短周期，可以在原始的两个模2加法器之间连接另外的模2加法器，附加的模2加法器在短时间段内反相信号的至少一个位。

6. 发明授权

US4011406A PCM regenerator 失效
标题翻译： PCM再生器
公开(公告)号：US4011406A
公开(公告)日：1977-03-08
申请号：US559631
申请日：1975-03-19
申请人： Reginhard Pospischil
发明人： Reginhard Pospischil
IPC分类号： H04L25/52 , H04L25/06 , H04L25/24 , H03K5/01 , H04L25/20
CPC分类号： H04L25/24 , H04L25/061
摘要： A PCM regenerator including an amplitude decision device, a time decision device which includes an input transformer with its secondary connected to a pair of transistors which form a push-pull circuit and wherein the output of directly consecutive pulses always have different polarities and accurately reconstructed pulses are produced.
摘要翻译：一种PCM再生器，包括幅度决定装置，时间决定装置，其包括输入变压器，其二次连接到形成推挽电路的一对晶体管，并且其中直接连续脉冲的输出总是具有不同的极性和精确重建的脉冲被生产。

7. 发明授权

US5123010A Method for the through-connection of multiplex signals via cross connectors 失效
标题翻译：用于通过交叉连接器进行多重信号连接的方法
公开(公告)号：US5123010A
公开(公告)日：1992-06-16
申请号：US539890
申请日：1990-06-18
申请人： Reginhard Pospischil
发明人： Reginhard Pospischil
IPC分类号： H04J3/00 , H04J3/06 , H04J3/07 , H04J3/16
CPC分类号： H04J3/0623 , H04J3/1611
摘要： Method for the through-connection of multiplex signals via cross-connectors, whereby the data of different multiplexing levels ordered in data blocks are converted into cross-connect data blocks that are ordered in a fixed superframe, whereby frequency deviations between external signals and the superframe are compensated by filling.
摘要翻译：用于通过交叉连接器直接连接多路复用信号的方法，由此在数据块中排列的不同复用级别的数据被转换成在固定超帧中排序的交叉连接数据块，由此外部信号与超帧之间的频率偏差通过填充补偿。

8. 发明授权

US4807290A Self-synchronizing scrambler 失效
标题翻译：自同步扰频器
公开(公告)号：US4807290A
公开(公告)日：1989-02-21
申请号：US784684
申请日：1985-09-25
申请人： Reginhard Pospischil
发明人： Reginhard Pospischil
IPC分类号： H04L25/49 , H04L7/00 , H04L25/03 , H04L25/48 , H04K1/02 , H04L9/04
CPC分类号： H04L25/03872
摘要： A self-synchronizing scrambler for high bit rates comprises a plurality of scrambler stages operating in parallel and which respectively represent the series connection of a first modulo-2 adder and a second modulo-2 adder and a shift register stage, whereby the output of the shift register stage is fed back to the input of the first modulo-2 adder of its own scrambler stage and the other input of the first modulo-2 adder is connected to a further scrambler stage.
摘要翻译： PCT No.PCT / DE85 / 00027 Sec。 371日期：1985年9月25日 102（e）1985年9月25日PCT提交1985年2月1日PCT公布。出版物WO85 / 03612 日期为1985年8月15日。用于高比特率的自同步扰频器包括并行操作的多个加扰器级，分别表示第一模2加法器和第二模2加法器和移位寄存器的串联连接从而将移位寄存器级的输出反馈到其自己的加扰器级的第一模2加法器的输入端，而第一模2加法器的另一输入端连接到另外的加扰器级。

9. 发明授权

US4797875A Method for monitoring and controlling the traffic in digital transmission networks 失效
标题翻译：监测和控制数字传输网络流量的方法
公开(公告)号：US4797875A
公开(公告)日：1989-01-10
申请号：US883375
申请日：1986-07-08
申请人： Reginhard Pospischil , Peter Breitfelder , Uwe Timmermann
发明人： Reginhard Pospischil , Peter Breitfelder , Uwe Timmermann
IPC分类号： H04M3/22 , H04M3/24 , H04M3/36 , H04Q3/00 , H04Q11/04 , H04J3/12 , H04J3/24
CPC分类号： H04Q11/04 , H04M3/2254 , H04M3/244 , H04M3/36 , H04Q3/0016
摘要： For monitoring and controlling the traffic in a transmission network of a multiplex hierarchy stage comprising circuit switching devices connected via digital signal sections, all digital signals to be fed in are supplied at their source with an identification character for a desired digital signal connection. The identification character is communicated to all involved circuit switching devices so that the same can be tracked along the digital signal connection and the circuit switching devices are correspondingly controlled. Idle digital signal sections can be maintained active with an alternate signal which contains an alternate signal identification character. Given a disturbance of a digital signal section, an alternate circuit can be switched.
摘要翻译：为了监测和控制包括经由数字信号部分连接的电路交换装置的多路复用层级级的传输网络中的业务，要馈送的所有数字信号在其源处以期望的数字信号连接的识别字符提供。识别字符被传送到所有相关的电路交换设备，使得可以沿着数字信号连接跟踪相同的电路交换设备，并且相应地控制电路交换设备。空闲的数字信号部分可以通过包含备用信号识别字符的交替信号保持有效。给定数字信号部分的干扰，可以切换交替电路。

10. 发明授权

US4669118A Self-synchronizing descrambler 失效
标题翻译：自同步解扰器
公开(公告)号：US4669118A
公开(公告)日：1987-05-26
申请号：US784685
申请日：1985-09-25
申请人： Reginhard Pospischil
发明人： Reginhard Pospischil
IPC分类号： H04L25/49 , H04L7/00 , H04L25/03 , H04L25/48 , H04K1/02 , H04L9/04
CPC分类号： H04L25/03872
摘要： For the purpose of suppressing DC components and high energy components at different frequencies, digital signals are frequently transmitted in scrambled form. The realization of corresponding scramblers and descramblers is involved and difficult at high transmission rates. A self-synchronizing descrambler is provided which, due to parallel processing of the digital signals to be descrambled, has a relatively low working speed and is easy to manufacture in integrated technology. The descrambler employs a plurality of descrambler stages each including first and second modulo-2 adders and a shift register stage.
摘要翻译： PCT No.PCT / DE85 / 00026 Sec。 371日期：1985年9月25日 102（e）1985年9月25日PCT提交1985年2月1日PCT公布。第WO85 / 03611号公报日期为1985年8月15日。为了抑制不同频率的直流分量和高能量分量，数字信号经常以加扰形式传输。相应的扰码器和解扰器的实现在高传输速率下是困难的。提供了一种自同步解扰器，由于要解扰的数字信号的并行处理，具有相对低的工作速度并且易于在集成技术中制造。解扰器采用多个解扰器级，每个解扰器级包括第一和第二模2加法器和移位寄存器级。

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