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1. 发明申请

WO0002249A3 INTEGRATED CIRCUIT WITH P-N JUNCTIONS WITH REDUCED DEFECTS 审中-公开
标题翻译： INTEGRATED CIRCUIT WITH P-N转变WITH减少的缺陷
公开(公告)号：WO0002249A3
公开(公告)日：2000-03-16
申请号：PCT/DE9901934
申请日：1999-07-01
申请人： SIEMENS AG , STENGL REINHARD , FRANOSCH MARTIN , SCHAEFER HERBERT , LEHMANN VOLKER , REISINGER HANS , WENDT HERMANN
发明人： STENGL REINHARD , FRANOSCH MARTIN , SCHAEFER HERBERT , LEHMANN VOLKER , REISINGER HANS , WENDT HERMANN
IPC分类号： H01L21/822 , H01L21/8242 , H01L27/04 , H01L27/108 , H01L29/04
CPC分类号： H01L27/10844 , H01L27/10805 , H01L29/045
摘要： The inventive integrated circuit comprises at least one first component with a structure to which defects may be adjacent and a second component with at least one p-n junction (Ü'), said components being situated next to each other in a substrate (1) whose defects extend in a defect plane (d) at least in sections. The crystal orientation of the substrate (1) in relation to the first component and the second component is chosen with the aim of keeping the defects on the surfaces without them intersecting the p-n junction (Ü'), in order to prevent undesirable leakage currents through the p-n junction (Ü'). The integrated circuit is especially a DRAM cell arrangement with extended retention time. The inventive integrated circuit is produced by mounting photo-resist masks of a known layout on the starting wafer, the masks being rotated in relation to a known starting wafer. Alternatively, photo-resist masks of a known layout can be mounted on a starting wafer in a conventional manner, the output wafer having a marking showing the course of the defect plane (d).
摘要翻译：所述集成电路装置包括至少在一个基片具有可以在邻近缺陷彼此相邻的结构，并且具有至少一个pn结（B“）的第二组分的第一组分（1）被布置，其至少缺陷部分中缺陷电平（d）延伸。被选择的衬底（1）相对于所述第一组分和所述第二组分的晶体取向，使得缺陷被记录在表面上而不被切断p-n结。以这种方式，能够避免通过p-n结（B“）不希望的泄漏。集成电路装置是特别具有增加的保留时间的DRAM单元的布置。为了制备集成电路装置光刻胶掩模可以被安装在一个已知的晶片布局相对于扭转的已知的起始晶片的输出。可替代地，光致抗蚀剂掩模的已知布局可以在输出晶片上以常规方式应用，但起始晶片具有示出的缺陷电平（d）的过程中的标签。

2. 发明申请

WO1998006140A1 METHOD OF OPERATING A STORAGE CELL ARRANGEMENT 审中-公开
标题翻译：一种用于操作存储器单元装置
公开(公告)号：WO1998006140A1
公开(公告)日：1998-02-12
申请号：PCT/DE1997001601
申请日：1997-07-29
申请人： SIEMENS AKTIENGESELLSCHAFT , REISINGER, Hans , STENGL, Reinhard , GRÜNING, Ulrike , WENDT, Hermann , WILLER, Josef , FRANOSCH, Martin , SCHÄFER, Herbert , KRAUTSCHNEIDER, Wolfgang , HOFMANN, Franz , LEHMANN, Volker , BÖHM, Thomas
发明人： SIEMENS AKTIENGESELLSCHAFT
IPC分类号： H01L29/792
CPC分类号： H01L29/513 , H01L29/518 , H01L29/792
摘要： The invention concerns a method of operating a storage cell arrangement having MOS transistors as storage cells which comprise, as gate dielectric, a triple dielectric layer (5) consisting of a first silicon oxide layer (51), a silicon nitride layer (52) and a second silicon oxide layer (53), each of the silicon oxide layers being at least 3 nm thick. According to the invention, in order to store digital data, a first threshold voltage value of the MOS transistor is allocated to a first logic value and a second threshold voltage value of the MOS transistor is allocated to a second logic value. The data stored in the storage cell can be altered by applying corresponding voltage levels, although complete removal of the charge stored in the silicon nitride layer is prevented by the thickness of the silicon oxide layers. The threshold voltage variation makes use of the fact that the electrical field in the triple dielectric layer is distorted by the charge stored in the silicon nitride layer.
摘要翻译：用于操作具有MOS晶体管作为存储单元的存储单元阵列，其包含作为栅极电介质，电介质三层（5），具有第一氧化硅层（51），氮化硅层（52）和第二氧化硅层（53），其中，所述氧化硅层厚3nm以上是，用于存储第一逻辑值，第一阈值电压值和第二逻辑值的数字数据被分配给该MOS晶体管的第二阈值电压值。存储在存储单元信息中的信息可以通过施加适当的电压电平被改变，即使在由于氧化硅的厚度的氮化硅层完全去除所存储的电荷的是不可能的。当改变该电场在电介质三层通过利用氮化硅膜所存储的电荷扭曲阈值电压。

3. 发明申请

WO1998006139A1 NON-VOLATILE STORAGE CELL 审中-公开
标题翻译：非易失性存储单元
公开(公告)号：WO1998006139A1
公开(公告)日：1998-02-12
申请号：PCT/DE1997001600
申请日：1997-07-29
申请人： SIEMENS AKTIENGESELLSCHAFT , REISINGER, Hans , STENGL, Reinhard , WENDT, Hermann , WILLER, Josef , LEHMANN, Volker , FRANOSCH, Martin , SCHÄFER, Herbert , KRAUTSCHNEIDER, Wolfgang , HOFMANN, Franz , GRÜNING, Ulrike
发明人： SIEMENS AKTIENGESELLSCHAFT
IPC分类号： H01L29/792
CPC分类号： H01L29/792 , H01L29/511
摘要： The invention concerns a non-volatile write-once storage cell comprising a MOS transistor which, as gate dielectric, has a triple dielectric layer consisting of a first silicon oxide layer (51), a silicon nitride layer (52) and a second silicon oxide layer (53). The first silicon oxide layer (51) and the second silicon oxide layer (53) are each at least 3 nm thick. The storage cell is not erasable and can hold data for a period of more than 1000 years.
摘要翻译：一种非易失性，一次写入存储器单元包括具有作为栅极电介质，电介质三层与第一氧化硅层（51）的MOS晶体管，硅氮化物层（52）和第二氧化硅层（53）。第一氧化硅层（51）和所述第二硅氧化物层（53）各自为至少3nm厚。该存储单元不能被删除，有时间保持超过1000年的数据。

4. 发明申请

WO2005050734A1 CHARGE-TRAPPING MEMORY DEVICE, OPERATING AND MANUFACTURING 审中-公开
标题翻译：充电跟踪存储器件，操作和制造
公开(公告)号：WO2005050734A1
公开(公告)日：2005-06-02
申请号：PCT/EP2004/012100
申请日：2004-10-26
申请人： INFINEON TECHNOLOGIES AG , LIAW, Corvin , MIKOLAJICK, Thomas , WILLER, Josef , REISINGER, Hans
发明人： LIAW, Corvin , MIKOLAJICK, Thomas , WILLER, Josef , REISINGER, Hans
IPC分类号： H01L21/8246
CPC分类号： H01L27/11568 , G11C16/0466 , G11C16/0491 , H01L21/28282 , H01L27/115 , H01L29/7923
摘要： The charge-trapping layer comprises two strips above the source and drain junctions. The thicknesses of the charge-trapping layer and the gate dielectric are chosen to facilitate Fowler-Nordheim-tunnelling of electrons into the strips during an erasure process. Programming is performed by injection of hot holes into the strips individually for two-bit storage.
摘要翻译：电荷捕获层包括在源极和漏极结上方的两个条带。选择电荷俘获层和栅极电介质的厚度，以便在擦除过程中促进Fowler-Nordheim隧穿隧道的电子。通过将热孔单独注入热孔进行两位存储来执行编程。

5. 发明申请

WO0036636A3 CAPACITOR ELECTRODE 审中-公开
标题翻译：电容电极
公开(公告)号：WO0036636A3
公开(公告)日：2000-08-10
申请号：PCT/DE9903926
申请日：1999-12-08
申请人： INFINEON TECHNOLOGIES AG , WENDT HERMANN , BEITEL GERHARD , REISINGER HANS
发明人： WENDT HERMANN , BEITEL GERHARD , REISINGER HANS
IPC分类号： H01L21/02 , H01L21/285 , H01L21/8242
CPC分类号： H01L28/75 , H01L28/55 , H01L28/60
摘要： The aim of the invention is to create a microelectronic structure which prevents oxidation of oxygen-sensitive structures (25). To this end, the microelectronic structure is provided with a conductive layer (10) consisting of a platinum iridium alloy. The iridium should hamper the oxygen diffusion through the conductive layer (10) by binding the oxygen when the microelectronic structure is treated in a oxygen-containing atmosphere. Oxidation-sensitive structures (25) are thus protected underneath the conductive layer (10).
摘要翻译：它是要创建的微电子结构，其防止对氧敏感的结构（25）的氧化。为了这个目的，在微电子结构的导电层（10）由铂铱合金制成。铱应通过结合氧气阻碍通过导电层（10）中的氧扩散，从而保护用一种处理微电子结构的导电层（10）下方的氧化敏感的结构（25）在含氧气氛。

6. 发明申请

WO1998027593A1 ARRANGEMENT FOR CONTROLLING PARALLEL LINES IN A STORAGE CELL ARRANGEMENT 审中-公开
标题翻译：布置，对于控制存储器单元装置平行线
公开(公告)号：WO1998027593A1
公开(公告)日：1998-06-25
申请号：PCT/DE1997002654
申请日：1997-11-12
申请人： SIEMENS AKTIENGESELLSCHAFT , HOFMANN, Franz , WILLER, Josef , REISINGER, Hans , VON BASSE, Paul, Werner , KRAUTSCHNEIDER, Wolfgang
发明人： SIEMENS AKTIENGESELLSCHAFT
IPC分类号： H01L27/112
CPC分类号： H01L27/0207 , H01L27/1126 , H01L27/11293 , H01L27/11803
摘要： In order to control parallel lines, for example bit lines (BLn) of a storage cell arrangement with doped regions in a semiconductor substrate, several lines (BLn) are electrically connected to one another and to a common node (K). Several selection lines (ALn) are provided transversely to the lines (BLn). At their crossing points are arranged MOS-transistors (M1, M2) mounted in series along one of the lines (BLn) and whose gate electrodes are formed by the corresponding selection line (ALn). At least one MOS-transistor (M1) in each of the parallel lines (BL1) has a higher operation voltage than the others.
摘要翻译：用于驱动的平行线，例如，位布置在包括掺杂区的半导体衬底的存储单元阵列的行（BLn的），多条线（BLn的）电连接在一起，并且至公共节点（K）。横向于所述线（BLn的）提供了多个选择线（ALN）。 MOS晶体管是在交叉点处（M1，M2）被布置，其中（BLn的）串联连接沿着线和栅电极中的一个通过相应的选择线（ALN）形成。至少一个MOS晶体管（M1）中的每个平行线的（BL1）具有比其他更高的阈值电压。

7. 发明申请

WO0045441A3 SEMICONDUCTOR DEVICE WITH A MULTIPLE DIELECTRIC 审中-公开
标题翻译：与MEHRFACHDIELEKTRIKUM半导体器件
公开(公告)号：WO0045441A3
公开(公告)日：2001-03-29
申请号：PCT/DE0000203
申请日：2000-01-25
申请人： INFINEON TECHNOLOGIES AG , BACHHOFER HARALD , REISINGER HANS , HANEDER THOMAS PETER
发明人： BACHHOFER HARALD , REISINGER HANS , HANEDER THOMAS PETER
IPC分类号： H01L29/51 , H01L21/28
CPC分类号： H01L29/511
摘要： The invention relates to a semiconductor device with a multiple dielectric, especially an ONO-triple dielectric, comprising a semiconductor substrate (10) of a first conduction type, a first doping area (20) of a second conduction type which is provided in said semiconductor substrate (10), a second doping area (30) of the second conduction type which is provided in the semiconductor substrate (10), a channel area (25) which is situated between the first and the second doping area (20, 30), a gate dielectric (40, 50, 60) which lies on top of the channel area (25) and which has at least three layers; and a gate terminal (70) which is provided on top of the gate dielectric (40, 50, 60). The bottom layer (40) of the gate dielectric (40, 50, 60) has an essentially smaller dielectric constant than the top layer (60) of the gate dielectric (40, 50, 60).
摘要翻译：本发明提供了一种具有Mehrfachdielektrikum的半导体器件，特别是ONO Dreifachdielektrikum，包括：第一导电类型的半导体衬底（10）; 一个在设置于第二导电型的第一杂质区（20）的半导体衬底（10）; 一个在设置于第二导电型的第二杂质区（30）的半导体衬底（10）; 一个所述第一和第二杂质区之间躺在（20，30）沟道区（25）; 一个在所述沟道区（25）下面的栅极电介质（40，50，60），其具有至少三个层; 及以上的栅极端子（70）设置在栅极电介质（40，50，60）。栅极电介质（40，50，60）的底部层（40）的介电常数比所述栅极电介质（40，50，60）的最上层（60）显着更小。

8. 发明申请

WO1998027586A1 METHOD FOR MANUFACTURING A MEMORY CELL CONFIGURATION 审中-公开
标题翻译：一种用于生产存储器单元装置
公开(公告)号：WO1998027586A1
公开(公告)日：1998-06-25
申请号：PCT/DE1997002549
申请日：1997-11-04
申请人： SIEMENS AKTIENGESELLSCHAFT , HOFMANN, Franz , WILLER, Josef , REISINGER, Hans , KRAUTSCHNEIDER, Wolfgang , VON BASSE, Paul-Werner
发明人： SIEMENS AKTIENGESELLSCHAFT
IPC分类号： H01L21/8246
CPC分类号： H01L27/112
摘要： In order to manufacture a memory cell configuration comprising a first series of memory cells including a vertical MOS transistor and a second series of memory cells without MOS transistor, the memory cells being arranged along the opposing flanks of strip-shaped pits, tiled memory cells are built one after the other along said pits (5). The spacing between the memory cells is determined according to a spacer technology enabling to meet the space need per memory cell, i.e. 1F , where F represents the minimum structural quantity specific to said technology.
摘要翻译：一种用于制造存储单元阵列，其包括具有垂直MOS晶体管第一存储单元，和第二存储单元，其没有晶体管MOS，所述存储单元被沿着带状沟槽的相对边缘布置是沿着连续相邻的存储单元之间的沟槽（5）产生的。相邻存储单元之间的距离是特别通过间隔技术确定。因此，每1F <2>的存储器单元的空间需求，可以实现，其中F是该技术的最小特征尺寸。

9. 发明申请

WO9965063A3 DRAM STORAGE CAPACITOR 审中-公开
标题翻译：存储器，用于电容器DRAM
公开(公告)号：WO9965063A3
公开(公告)日：2000-03-16
申请号：PCT/DE9901454
申请日：1999-05-12
申请人： SIEMENS AG , REISINGER HANS , LEHMANN VOLKER , STENGL REINHARD , WENDT HERMANN , LANGE GERRIT , BACHHOFER HARALD , FRANOSCH MARTIN , SCHAEFER HERBERT
发明人： REISINGER HANS , LEHMANN VOLKER , STENGL REINHARD , WENDT HERMANN , LANGE GERRIT , BACHHOFER HARALD , FRANOSCH MARTIN , SCHAEFER HERBERT
IPC分类号： H01L21/8242 , H01L27/108
CPC分类号： H01L27/1085 , H01L27/10805
摘要： (57) Abstract The invention relates to a DRAM storage capacitor, comprising a dielectric made of silicon nitride and at least two electrodes placed opposite to each other above the dielectric. A material with higher tunnel barrier ( phi beta ) between the Fermi level (F) of the material and the conduction band (L) of the dielectric is used for the electrodes. For said purpose, the appropriate materials are metals such a platinum, tungsten and iridium or silicide. (57) Zusammenfassung Die Erfindung betrifft einen Speicherkondensator für einen DRAM, mit einem aus Siliziumnitrid bestehenden Dielektrikum und mit wenigstens zwei, über das Dielektrikum einander gegenüberliegenden Elektroden. Für die Elektroden wird ein Material mit hoher Tunnelbarriere ( phi beta ) zwischen Fermi-Niveau (F) des Materials und Leitungsband (L) des Dielektrikums verwendet. Geeignete Materialien sind hierfür Metalle wie Platin, Wolfram und Iridium oder Silizide.
摘要翻译：本发明涉及一种存储电容器用于DRAM，包括由氮化硅的电介质构成的组，和具有至少两个电极在所述电介质彼此相对。对于使用电介质的材料具有高的隧道势垒（PHI测试版）的材料和导带（L）的费米能级（F）之间的电极。用于此目的的合适的材料是金属，例如铂，钨，和铱，或硅化物。

10. 发明申请

WO1998027594A1 MEMORY CELL ARRANGEMENT AND PROCESS FOR MANUFACTURING THE SAME 审中-公开
标题翻译：存储器单元装置和方法及其
公开(公告)号：WO1998027594A1
公开(公告)日：1998-06-25
申请号：PCT/DE1997002730
申请日：1997-11-20
申请人： SIEMENS AKTIENGESELLSCHAFT , HOFMANN, Franz , WILLER, Josef , REISINGER, Hans , VON BASSE, Paul-Werner , KRAUTSCHNEIDER, Wolfgang
发明人： SIEMENS AKTIENGESELLSCHAFT
IPC分类号： H01L27/115
CPC分类号： H01L27/11568 , H01L21/28282 , H01L27/115 , H01L27/11517
摘要： Several mutually insulated memory cell lines arranged in a semiconductor substrate (21) include each a first doped region (D1') and a second doped region (D2') between which are arranged a gate dielectric (29, 32) which contains a material with charge carriers capturing points and several gate electrodes (WL1', WL2'). The distance between adjacent gate electrodes (WL1', WL2') is smaller than the dimensions of the gate electrodes (WL1', WL2'). Information is stored by introducing charge carriers into the gate dielectric (29, 32). The gate electrodes (WL1', WL2') are preferably produced by a spacer technique.
摘要翻译：在半导体基板（21）上设置有多个互相绝缘的收容单元列，每个具有包括具有材料的载流子的第一掺杂区域（D1“）和第二掺杂区（D2”），在它们之间的栅极电介质（29，32）含有粘附位点，以及多个栅电极（WL1”，WL2' ）被布置。相邻的栅电极（WL1”，WL2‘）之间的距离比栅电极的尺寸更小（WL1’，WL2' ）。的信息是由引入的电荷载流子进入Gatedieletrikum（29，32）被存储。栅电极（WL1”，WL2' ）优选地通过间隔技术制备。

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