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    • 1. 发明申请
    • A JTAG TESTING ARRANGEMENT FOR AN INTEGRATED CIRCUIT
    • 集成电路的JTAG测试安排
    • WO2007042622A1
    • 2007-04-19
    • PCT/FI2006/050438
    • 2006-10-12
    • PATRIA SYSTEMS OYSIMONEN, MikkoREIS, Ilkka
    • SIMONEN, MikkoREIS, Ilkka
    • G01R31/3185G01R31/319
    • G01R31/318519G01R31/318558
    • The invention relates to an integrated circuit (IC) comprising a core function block (FC) and a first chain of boundary-scan cells (BSC1- BSC12) implemented around it, and a state machine (FSM) controlling the same. The integrated circuit also comprises a second chain of boundary-scan cells (PBSC1-PBSC6) implemented between the core function block (FC) of the integrated circuit and said first chain of boundary-scan cells (BSC1-BSC12), or as a part of the core function block (FC) of the circuit, at least partly in parallel with said first chain of boundary-scan cells; a test interface (IO-TDO, IO-TMS, IO-TCK, IO-TDI; TAP) adapted to said second chain of boundary-scan cells; and a second state machine (PFSM) arranged to control said second chain of boundary-scan cells.
    • 本发明涉及包括核心功能块(FC)和在其周围实现的第一边界扫描单元链(BSC-BSC12)的集成电路(IC)和控制该集成电路的状态机(FSM)。 集成电路还包括实现在集成电路的核心功能块(FC)和所述第一边界扫描单元链(BSC1-BSC12)之间的第二条边界扫描单元(PBSC1-PBSC6),或作为部分 所述电路的核心功能块(FC)至少部分地与所述第一边界扫描单元链平行; 适于所述第二边界扫描单元链的测试接口(IO-TDO,IO-TMS,IO-TCK,IO-TDI; TAP) 以及布置成控制所述第二边界扫描单元链的第二状态机(PFSM)。
    • 2. 发明申请
    • JTAG TESTING ARRANGEMENT
    • JTAG测试安排
    • WO2004046741A1
    • 2004-06-03
    • PCT/FI2003/000893
    • 2003-11-20
    • PATRIA NEW TECHNOLOGIES OYREIS, IlkkaSIMONEN, Mikko
    • REIS, IlkkaSIMONEN, Mikko
    • G01R31/3181
    • G01R31/318555G01R31/3025G01R31/318533G01R31/318572
    • JTAG test equipment arranged to establish an asynchronous data transmission connection with a JTAG-compatible device under test for the transmission of test data between test access ports (TAP) in the test equipment and device under test. The test data is synchronized at reception before the test access ports (TAP). The test equipment comprises means (A(up)) implemented as a computer program for adapting a test data sequence arriving in the format defined by the test access port for transmission on an asynchronous transmission path, and a transceiver (TR1) for adapting the test data sequence and transmitting it through the asynchronous data transmission connection to the device under test.
    • JTAG测试设备被布置成与被测试的JTAG兼容设备建立异步数据传输连接,用于在测试设备和被测设备中的测试访问端口(TAP)之间传输测试数据。 在测试访问端口(TAP)之前,测试数据在接收时同步。 测试设备包括实现为计算机程序的装置(A(up)),用于使以由测试访问端口定义的格式到达的测试数据序列用于在异步传输路径上传输;以及收发器(TR1),用于使测试 数据序列,并将其通过异步数据传输连接发送到被测设备。