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1. 发明申请

WO2014106781A1 SECRETS RENEWABILITY 审中-公开
标题翻译：秘密可再生能力
公开(公告)号：WO2014106781A1
公开(公告)日：2014-07-10
申请号：PCT/IB2013/055658
申请日：2013-07-10
申请人： NDS LIMITED , KARA-IVANOV, Michael , KIPNIS, Aviad , REINMAN, Tzachy , MANGELL, Efraim , WAISBARD, Erez , BELENKY, Yaacov
发明人： KARA-IVANOV, Michael , KIPNIS, Aviad , REINMAN, Tzachy , MANGELL, Efraim , WAISBARD, Erez , BELENKY, Yaacov
IPC分类号： H04L9/08
CPC分类号： H04L9/0861 , H04L9/0869
摘要： A method, system and apparatus for deriving a secondary secret from a root secret are described, the method, system and apparatus including reserving a memory buffer included in an integrated circuit, the memory buffer being large enough to contain all of the bits which will include the secondary secret, receiving a plurality of bits from a root secret, the root secret being stored in a secure memory of the integrated circuit, inputting the plurality of bits from the root secret and at least one control bit into a permutation network, and thereby producing a multiplicity of output bits, the at least one control bit including one of one bit of a value g, and one bit an output of a function which receives g as an input, receiving the multiplicity of output bits from the permutation network, inputting the multiplicity of output bits from the permutation network into a plurality of logic gates, thereby combining the multiplicity of output bits, wherein a fixed number of bits is output from the logic gates, inputting the fixed number of bits output by the logic gates into an error correcting code module, the fixed number of bits output by the logic gates including a first group of intermediate output bits and a second group of intermediate output bits and receiving output bits from the error correcting code module, the output bits of the error correcting code module including the first group of intermediate output bits as changed by the error correcting code module, where the change depends on the second group of intermediate output bits, filling non-filled registers in the reserved memory buffer with the first group of intermediate output bits as changed by the error correcting code module, and repeating the steps of "receiving a plurality of bits from a root secret" through "filling non-filled registers in the reserved memory buffer" until the entire secondary secret is derived, wherein the steps of "receiving a plurality of bits from a root secret" through "filling non-filled registers in the reserved memory buffer" are performed in a single clock cycle of the integrated circuit. Related apparatus, methods and systems are also described.
摘要翻译：描述了用于从根秘密导出第二秘密的方法，系统和装置，所述方法，系统和装置包括保留包括在集成电路中的存储器缓冲器，所述存储器缓冲器足够大以包含将包括的所有位第二秘密，从根秘密接收多个比特，根秘密被存储在集成电路的安全存储器中，从根秘密输入多个比特和至少一个控制比特进入置换网络，从而产生多个输出比特，所述至少一个控制比特包括值g的一个比特中的一个，一个比特作为接收g作为输入的函数的输出，从置换网络接收多个输出比特，输入从置换网络到多个逻辑门的多个输出比特，从而组合多个输出比特，其中固定比特数从逻辑门，将由逻辑门输出的固定位数输入到纠错码模块中，逻辑门输出的固定位数包括第一组中间输出位和第二组中间输出位，并接收来自纠错码模块的输出位，纠错码模块的输出位包括由纠错码模块改变的第一组中间输出位，其中改变取决于第二组中间输出位，所述预留存储器缓冲器中的所述第一组中间输出位的补充寄存器被所述纠错码模块改变，并且重复“从根秘密接收多个位”的步骤，通过“将未填充寄存器保留的存储器缓冲器“，直到导出完整的二级秘密，其中”通过“不填入”从“根秘密接收多个比特” 在保留的存储器缓冲器中的n个填充寄存器“在集成电路的单个时钟周期中执行。还描述了相关装置，方法和系统。

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