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1. 发明申请

WO2014099032A1 PACKAGE STRUCTURES INCLUDING DISCRETE ANTENNAS ASSEMBLED ON A DEVICE 审中-公开
标题翻译：包装结构包括在装置上组装的离散天线
公开(公告)号：WO2014099032A1
公开(公告)日：2014-06-26
申请号：PCT/US2013/048671
申请日：2013-06-28
申请人： INTEL CORPORATION , KAMGAING, Telesphor , RAO, Valluri R. , DEGANI, Ofir
发明人： KAMGAING, Telesphor , RAO, Valluri R. , DEGANI, Ofir
IPC分类号： H01Q1/38 , H01Q1/24
CPC分类号： H01Q9/045 , H01L2224/16225 , H01L2924/15311 , H01P11/00 , H01Q1/2283 , H01Q1/38 , H01Q1/526 , H01Q21/0006 , Y10T29/49018
摘要： Methods of forming a microelectronic packaging structure and associated structures formed thereby are described. Those methods and structures may include forming a package structure comprising a discrete antenna disposed on a back side of a device, wherein the discrete antenna comprises an antenna substrate, a through antenna substrate via vertically disposed through the antenna substrate. A through device substrate via that is vertically disposed within the device is coupled with the through antenna substrate via, and a package substrate is coupled with an active side of the device.
摘要翻译：描述了形成微电子封装结构的方法及由此形成的相关结构。这些方法和结构可以包括形成包括设置在设备的背侧的分立天线的封装结构，其中分立天线包括天线基板，通过天线基板垂直设置的通过天线基板。垂直设置在器件内的穿通器件衬底通孔经由天线衬底与封装衬底耦合，并且封装衬底与器件的有源侧耦合。

2. 发明申请

WO2008002943A1 BIT-ERASING ARCHITECTURE FOR SEEK-SCAN PROBE (SSP) MEMORY STORAGE 审中-公开
标题翻译： SEEK-SCAN PROBE（SSP）存储器的BIT-ERASING ARCHITECTURE
公开(公告)号：WO2008002943A1
公开(公告)日：2008-01-03
申请号：PCT/US2007/072163
申请日：2007-06-26
申请人： INTEL CORPORATION , MA, Qing , RAO, Valluri, R. , CHOU, Tsung-kuan, Allen
发明人： MA, Qing , RAO, Valluri, R. , CHOU, Tsung-kuan, Allen
IPC分类号： H01L27/115 , H01L21/8247
CPC分类号： B82Y10/00 , G11B9/04 , G11B9/1436 , G11B9/1472
摘要： An apparatus comprising a substrate, a heater formed on the substrate, and a phase-change layer formed on the heater. The heater comprises a heater layer and first and second electrodes electrically coupled to the heater layer. A process comprising forming a heater on a substrate and forming a phase-change layer on the heater. The heater comprises a heater layer and first and second electrodes electrically coupled to the heater layer.
摘要翻译：一种包括基板，形成在基板上的加热器和形成在加热器上的相变层的装置。加热器包括加热器层和电耦合到加热器层的第一和第二电极。一种方法，包括在基底上形成加热器并在加热器上形成相变层。加热器包括加热器层和电耦合到加热器层的第一和第二电极。

3. 发明申请

WO2018004696A1 ALIGNMENT OF SINGLE AND MULTI-MODE OPTICAL FIBERS USING PIEZOELECTRIC ACTUATORS 审中-公开
标题翻译：使用压电执行器来调整单模和多模光纤
公开(公告)号：WO2018004696A1
公开(公告)日：2018-01-04
申请号：PCT/US2016/040871
申请日：2016-07-01
申请人： INTEL CORPORATION , SWAN, Johanna M. , ALEKSOV, Aleksandar , OSTER, Sasha N. , EID, Feras , BICEN, Baris , SOUNART, Thomas L. , LIFF, Shawna M. , RAO, Valluri R.
发明人： SWAN, Johanna M. , ALEKSOV, Aleksandar , OSTER, Sasha N. , EID, Feras , BICEN, Baris , SOUNART, Thomas L. , LIFF, Shawna M. , RAO, Valluri R.
IPC分类号： G02B6/26 , G02B6/35 , G02B6/36
摘要： Embodiments of the invention include an optoelectronic package that allows for in situ alignment of optical fibers. In an embodiment, the optoelectronic package may include an organic substrate. Embodiments include a cavity formed into the organic substrate. Additionally, the optoelectronic package may include an actuator formed on the organic substrate that extends over the cavity. In one embodiment, the actuator may include a first electrode, a piezoelectric layer formed on the first electrode, and a second electrode formed on the piezoelectric layer. According to an additional embodiment of the invention, the actuator may include a first portion and a second portion. In order to allow for resistive heating and actuation driven by thermal expansion, a cross-sectional area of the first portion of the beam may be greater than a cross-sectional area of the second portion of the beam.
摘要翻译：本发明的实施例包括允许光纤原位对准的光电子封装。在一个实施例中，光电子封装可以包括有机衬底。实施例包括形成在有机衬底中的空腔。另外，光电子封装可以包括在有机衬底上形成的致动器，其在腔体上延伸。在一个实施例中，致动器可以包括第一电极，形成在第一电极上的压电层以及形成在压电层上的第二电极。根据本发明的另外的实施例，致动器可以包括第一部分和第二部分。为了允许由热膨胀驱动的电阻加热和致动，梁的第一部分的横截面积可以大于梁的第二部分的横截面积。

4. 发明申请

WO2012151003A3 CHIP PACKAGES INCLUDING THROUGH-SILICON VIA DICE WITH VERTICALLY INTEGRATED PHASED-ARRAY ANTENNAS AND LOW-FREQUENCY AND POWER DELIVERY SUBSTRATES 审中-公开
标题翻译：芯片包装，包括通过硅片与垂直集成的相位阵列天线和低频和电力输送基板
公开(公告)号：WO2012151003A3
公开(公告)日：2013-03-14
申请号：PCT/US2012029363
申请日：2012-03-16
申请人： INTEL CORP , KAMGAING TELESPHOR , RAO VALLURI R , PALASKAS YORGOS
发明人： KAMGAING TELESPHOR , RAO VALLURI R , PALASKAS YORGOS
IPC分类号： H01L23/48
CPC分类号： H01Q3/30 , H01L23/66 , H01L25/0657 , H01L25/16 , H01L25/18 , H01L2223/6677 , H01L2224/13025 , H01L2224/14181 , H01L2224/16145 , H01L2224/16225 , H01L2225/06513 , H01L2225/06517 , H01L2924/15321 , H01Q1/2283 , H01Q9/0414 , H01Q21/065 , H01Q23/00 , Y10T29/49004 , Y10T29/49018
摘要： An apparatus includes a die with through-silicon vias and radio frequency integrated circuit capabilities and it is vertically integrated with a phased-array antenna substrate. The through-silicon via and a radio frequency integrated circuit is coupled to a plurality of antenna elements disposed on the phased-array antenna substrate where each of the plurality of antenna elements is coupled to the through-silicon vias and radio frequency integrated circuit through a plurality of through-silicon vias. A process of assembling the through-silicon vias and radio frequency integrated circuit to the phased-array antenna substrate includes testing the apparatus.
摘要翻译：一种装置包括具有通硅通孔和射频集成电路功能的裸片，并且与相控阵天线基板垂直集成。穿硅通孔和射频集成电路耦合到布置在相控阵天线基板上的多个天线元件，其中多个天线元件中的每一个天线元件通过一个通孔硅通孔和射频集成电路多个通硅通孔。将穿硅通孔和射频集成电路组装到相控阵天线基板的过程包括测试该装置。

5. 发明申请

WO2012151120A2 RADIO- AND ELECTROMAGNETIC INTERFERENCE THROUGH-SILICON VIAS FOR STACKED-DIE PACKAGES, AND METHODS OF MAKING SAME 审中-公开
标题翻译：用于堆叠式包装的通过硅电缆的无线电和电磁干扰及其制造方法
公开(公告)号：WO2012151120A2
公开(公告)日：2012-11-08
申请号：PCT/US2012/035373
申请日：2012-04-27
申请人： INTEL CORPORATION , KAMGAING, Telesphor , RAO, Valluri R.
发明人： KAMGAING, Telesphor , RAO, Valluri R.
IPC分类号： H01L23/66 , H05K9/00
CPC分类号： H01L23/552 , H01L23/481 , H01L23/66 , H01L25/18 , H01L2223/6616 , H01L2223/6677 , H01L2224/16225 , H01L2225/06513 , H01L2225/06537 , H01L2225/06541 , H01L2924/15311
摘要： An apparatus includes a radio-frequency die with shielding through-silicon vias and a die backside lattice lid that shield a sector in the RF die from radio - and electromagnetic interference.
摘要翻译：一种装置包括具有屏蔽通硅通孔的射频管芯和屏蔽RF管芯中的扇区的模具背面格栅盖与无线电和电磁干扰。

6. 发明申请

WO2011084235A3 GLASS CORE SUBSTRATE FOR INTEGRATED CIRCUIT DEVICES AND METHODS OF MAKING THE SAME 审中-公开
标题翻译：用于集成电路器件的玻璃芯基板及其制造方法
公开(公告)号：WO2011084235A3
公开(公告)日：2011-09-09
申请号：PCT/US2010056310
申请日：2010-11-11
申请人： INTEL CORP , MA QING , RAO VALLURI R , TRAN QUAN A , SANKMAN ROBERT L , SWAN JOHANNA M
发明人： MA QING , RAO VALLURI R , TRAN QUAN A , SANKMAN ROBERT L , SWAN JOHANNA M
IPC分类号： H01L23/485 , H01L21/60
CPC分类号： H05K1/112 , H01L21/4803 , H01L21/486 , H01L23/15 , H01L23/3675 , H01L23/49822 , H01L23/49827 , H01L2224/16225 , H01L2224/16227 , H01L2224/32245 , H01L2224/73253 , H01L2924/00014 , H01L2924/10253 , H05K3/0014 , H05K3/4605 , H05K3/4644 , H05K2201/096 , H05K2201/09827 , H05K2201/10287 , H05K2201/10371 , H05K2201/10674 , H05K2203/0108 , H05K2203/0228 , H05K2203/025 , Y10T29/49117 , Y10T29/49126 , Y10T29/49155 , H01L2924/00 , H01L2224/0401
摘要： Disclosed are embodiments of a glass core substrate for an integrated circuit (IC) device. The glass core substrate includes a glass core and build-up structures on opposing sides of the glass core. Electrically conductive terminals may be formed on both sides of the glass core substrate. An IC die may be coupled with the terminals on one side of the substrate, whereas the terminals on the opposing side may be coupled with a next-level component, such as a circuit board. The glass core may comprise a single piece of glass in which conductors have been formed, or the glass core may comprise two or more glass sections that have been joined together, each section having conductors. The conductors extend through the glass core, and one or more of the conductors may be electrically coupled with the build-up structures disposed over the glass core. Other embodiments are described and claimed.
摘要翻译：公开了用于集成电路（IC）装置的玻璃芯基板的实施例。玻璃芯基板包括玻璃芯和在玻璃芯的相对侧上的堆积结构。导电端子可以形成在玻璃芯基板的两侧。 IC管芯可以与衬底的一侧上的端子耦合，而相对侧上的端子可以与诸如电路板的下一级组件耦合。玻璃芯可以包括其中已经形成有导体的单片玻璃，或者玻璃芯可以包括已经接合在一起的两个或更多个玻璃部分，每个部分具有导体。导体延伸穿过玻璃芯，并且一个或多个导体可以与布置在玻璃芯上的积层结构电耦合。描述并要求保护其他实施例。

7. 发明申请

WO2011084235A2 GLASS CORE SUBSTRATE FOR INTEGRATED CIRCUIT DEVICES AND METHODS OF MAKING THE SAME 审中-公开
标题翻译：用于集成电路装置的玻璃核心基板及其制造方法
公开(公告)号：WO2011084235A2
公开(公告)日：2011-07-14
申请号：PCT/US2010/056310
申请日：2010-11-11
申请人： INTEL CORPORATION , MA, Qing , RAO, Valluri R. , TRAN, Quan A. , SANKMAN, Robert L. , SWAN, Johanna M.
发明人： MA, Qing , RAO, Valluri R. , TRAN, Quan A. , SANKMAN, Robert L. , SWAN, Johanna M.
IPC分类号： H01L23/485 , H01L21/60
CPC分类号： H05K1/112 , H01L21/4803 , H01L21/486 , H01L23/15 , H01L23/3675 , H01L23/49822 , H01L23/49827 , H01L2224/16225 , H01L2224/16227 , H01L2224/32245 , H01L2224/73253 , H01L2924/00014 , H01L2924/10253 , H05K3/0014 , H05K3/4605 , H05K3/4644 , H05K2201/096 , H05K2201/09827 , H05K2201/10287 , H05K2201/10371 , H05K2201/10674 , H05K2203/0108 , H05K2203/0228 , H05K2203/025 , Y10T29/49117 , Y10T29/49126 , Y10T29/49155 , H01L2924/00 , H01L2224/0401
摘要： Disclosed are embodiments of a glass core substrate for an integrated circuit (IC) device. The glass core substrate includes a glass core and build-up structures on opposing sides of the glass core. Electrically conductive terminals may be formed on both sides of the glass core substrate. An IC die may be coupled with the terminals on one side of the substrate, whereas the terminals on the opposing side may be coupled with a next-level component, such as a circuit board. The glass core may comprise a single piece of glass in which conductors have been formed, or the glass core may comprise two or more glass sections that have been joined together, each section having conductors. The conductors extend through the glass core, and one or more of the conductors may be electrically coupled with the build-up structures disposed over the glass core. Other embodiments are described and claimed.
摘要翻译：公开了用于集成电路（IC）装置的玻璃芯基板的实施例。玻璃芯基板包括在玻璃芯的相对侧上的玻璃芯和堆积结构。导电端子可以形成在玻璃芯基板的两侧。 IC芯片可以与衬底的一侧上的端子耦合，而相对侧上的端子可以与诸如电路板的下一级组件耦合。玻璃芯可以包括其中已经形成导体的单片玻璃，或者玻璃芯可以包括已经连接在一起的两个或更多个玻璃部分，每个部分具有导体。导体延伸穿过玻璃芯，并且一个或多个导体可以与设置在玻璃芯上的积聚结构电耦合。描述和要求保护其他实施例。

8. 发明申请

WO2007078646A1 FREQUENCY TUNING OF FILM BULK ACOUSTIC RESONATORS (FBAR) 审中-公开
标题翻译：薄膜音箱谐振器（FBAR）的频率调谐
公开(公告)号：WO2007078646A1
公开(公告)日：2007-07-12
申请号：PCT/US2006/047138
申请日：2006-12-06
申请人： INTEL CORPORATION , RAO, Valluri, R. , DOROS, Theodore, G. , MA, Qing , SESHAN, Krishna , WANG, Li-Peng
发明人： RAO, Valluri, R. , DOROS, Theodore, G. , MA, Qing , SESHAN, Krishna , WANG, Li-Peng
IPC分类号： H03H3/04 , H03H9/58 , H03H9/17 , H03H9/02
CPC分类号： H03H3/04 , H03H3/0076 , H03H2003/0428 , H03H2003/0478
摘要： Multiple FBARs may be manufactured on a single wafer and later diced. Ideally, all devices formed in a wafer would have the same resonance frequency. However, due to manufacturing variances, the frequency response of the FBAR devices may vary slightly across the wafer. An RF map may be created to determine zones (50, 52) over the wafer where FBARs in that zone all vary from a target frequency by a similar degree. A tuning layer (40) may be deposited over the wafer. Lithographically patterned features to the tuning layer based on the zones identified by the RF map may be used to correct the FBARs to a target resonance frequency with the FBARs still intact on the wafer.
摘要翻译：多个FBAR可以在单个晶片上制造并且稍后被切割。理想地，形成在晶片中的所有器件将具有相同的谐振频率。然而，由于制造方差，FBAR器件的频率响应可能会在晶圆上略有不同。可以创建RF映射以确定晶片上的区域（50,52），其中该区域中的FBAR全部从目标频率变化相似程度。调谐层（40）可以沉积在晶片上。可以使用基于由RF映射表示的区域的调谐层的光刻图案特征来将FBAR校正到目标谐振频率，同时FBAR在晶片上仍然完整。

9. 发明申请

WO2017147892A1 OPERATING INTERNET OF THINGS DEVICES USING LiDAR METHOD AND APPARATUS 审中-公开
标题翻译：使用激光雷达方法和设备操作这些设备的互联网
公开(公告)号：WO2017147892A1
公开(公告)日：2017-09-08
申请号：PCT/CN2016/075588
申请日：2016-03-04
申请人： INTEL CORPORATION , ZHOU, Zhen , HAN, Ke , RAO, Valluri R. , ENG, Jonathan
发明人： ZHOU, Zhen , HAN, Ke , RAO, Valluri R. , ENG, Jonathan
IPC分类号： G06F3/01
CPC分类号： G06F3/017
摘要： Techniques and configurations for an apparatus(100) for controlling IoT devices(110, 112, 114) are provided. In one instance, an apparatus (100) may include a LiDAR scanner (102) having a laser (104) to scan (106) an environment(108) to obtain scan data. Scanning may include illuminating a point of the environment (108) and measuring a distance to that point based on a difference between a time of transmission of a beam to illuminate the point and a time of receipt of a beam reflected by the point. The apparatus (100) may further include a controller (130) to collect and analyze the scan data, detect a presence of a user (120, 122, 124) in the environment (108), detect and identify a gesture provided by the user (120, 122, 124 ), and provide a command to one or more IoT devices (110, 112, 114) that are responsive to commands provided by user gestures, based in part on the identified gesture.
摘要翻译：提供了用于控制IoT设备（110,112,114）的设备（100）的技术和配置。在一个实例中，装置（100）可以包括具有激光器（104）以扫描（106）环境（108）以获得扫描数据的LiDAR扫描仪（102）。扫描可以包括照亮环境的点（108）并且基于照射该点的光束的传输时间与接收由该点反射的光束的时间之间的差来测量到该点的距离。装置（100）还可以包括控制器（130），用于收集和分析扫描数据，检测环境（108）中的用户（120,122,124）的存在，检测并识别由用户提供的手势（120,122,124），并且部分地基于所识别的手势向响应于由用户手势提供的命令的一个或多个IoT设备（110,112,114）提供命令。

10. 发明申请

WO2015142322A1 SEMICONDUCTOR ASSEMBLIES WITH FLEXIBLE SUBSTRATES 审中-公开
标题翻译：具有柔性基板的半导体组件
公开(公告)号：WO2015142322A1
公开(公告)日：2015-09-24
申请号：PCT/US2014/031094
申请日：2014-03-18
申请人： INTEL CORPORATION , MUKHERJEE, Niloy , DOYLE, Brian, S. , DASGUPTA, Sansaptak , RADOSAVLJEVIC, Marko , PILLARISETTY, Ravi , THEN, Han Wui , RAO, Valluri, R. , CHAU, Robert, S.
发明人： MUKHERJEE, Niloy , DOYLE, Brian, S. , DASGUPTA, Sansaptak , RADOSAVLJEVIC, Marko , PILLARISETTY, Ravi , THEN, Han Wui , RAO, Valluri, R. , CHAU, Robert, S.
IPC分类号： H01L29/04 , H01L21/763
CPC分类号： H01L21/02513 , H01L21/02164 , H01L21/02178 , H01L21/02186 , H01L21/0228 , H01L21/02282 , H01L21/02422 , H01L21/02428 , H01L21/02488 , H01L21/02521 , H01L21/02532 , H01L21/02538 , H01L21/02549 , H01L21/02551 , H01L21/02595 , H01L21/02631 , H01L21/02675 , H01L21/763 , H01L27/1218 , H01L27/1225 , H01L29/78603 , H01L29/78681
摘要： Embodiments of semiconductor assemblies, and related integrated circuit devices and techniques, are disclosed herein. In some embodiments, a semiconductor assembly may include a flexible substrate, a polycrystalline semiconductor material, and a polycrystalline dielectric disposed between and adjacent to the flexible substrate and the polycrystalline semiconductor material. The polycrystalline semiconductor material may include a polycrystalline III-V material, a polycrystalline II-VI material or polycrystalline germanium. Other embodiments may be disclosed and/or claimed.
摘要翻译：本文公开了半导体组件的实施例以及相关的集成电路器件和技术。在一些实施例中，半导体组件可以包括柔性衬底，多晶半导体材料和布置在柔性衬底和多晶半导体材料之间和之后的多晶电介质。多晶半导体材料可以包括多晶III-V材料，多晶II-VI材料或多晶锗。可以公开和/或要求保护其他实施例。

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