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1. 发明授权

US06496967B1 Method of datapath cell placement for an integrated circuit 有权
标题翻译：集成电路数据通道单元放置方法
公开(公告)号：US06496967B1
公开(公告)日：2002-12-17
申请号：US09805642
申请日：2001-03-13
申请人： Alexander Tetelbaum , Qiong J. Yu
发明人： Alexander Tetelbaum , Qiong J. Yu
IPC分类号： G06F945
CPC分类号： G06F17/5072
摘要： A method of datapath cell placement is disclosed that minimizes signal propagation time through a datapath macro and datapath macro area that includes the steps of receiving a datapath description of constrained input pins, unconstrained input pins, and output pins for a datapath block; assigning a first corresponding first cell level to a first datapath cell in a data path of a constrained input pin wherein the first corresponding first cell level is representative of a number of intervening datapath cells between the first datapath cell and the constrained input pin; assigning a second corresponding first cell level to a second datapath cell in a data path connecting the first datapath cell to an unconstrained input pin that is substantially identical to the first corresponding first cell level; and assigning a corresponding second cell level to the datapath cell in the data path connecting the first datapath cell to the unconstrained input pin wherein the second cell level is representative of a number of intervening datapath cells between the datapath cell in the data path of the unconstrained input pin and the unconstrained input pin.
摘要翻译：公开了一种数据通路单元放置的方法，其通过数据路径宏和数据路径宏区域最小化信号传播时间，其包括以下步骤：接收数据路径块的约束输入引脚，非约束输入引脚和输出引脚的数据路径描述; 将第一对应的第一单元级别分配给约束输入引脚的数据路径中的第一数据路径单元，其中所述第一对应的第一单元级代表所述第一数据路径单元和所述约束输入引脚之间的中间数据路径单元的数量; 将第二对应的第一单元级别分配给连接第一数据路径单元与基本上与第一对应的第一单元级相同的非约束输入引脚的数据路径中的第二数据路径单元; 以及将相应的第二小区级分配给连接所述第一数据路由小区与所述无约束输入引脚的所述数据路径中的所述数据路径小区，其中所述第二小区级别表示所述无约束的数据路径中的所述数据路由小区之间的中间数据路由小区的数量输入引脚和无约束输入引脚。

2. 发明授权

US06829754B1 Method and system for checking for power errors in ASIC designs 失效
标题翻译：用于检查ASIC设计中功率误差的方法和系统
公开(公告)号：US06829754B1
公开(公告)日：2004-12-07
申请号：US10163208
申请日：2002-06-04
申请人： Qiong J. Yu , Radoslav M. Ratchkov , Bo Shen , Prasad Subbarao , Thomas M. Antisseril , Charutosh Dixit , Julie L. Beatty
发明人： Qiong J. Yu , Radoslav M. Ratchkov , Bo Shen , Prasad Subbarao , Thomas M. Antisseril , Charutosh Dixit , Julie L. Beatty
IPC分类号： G06F1750
CPC分类号： G06F17/5081 , G06F2217/78 , Y10S707/99943
摘要： A method for checking power errors in an ASIC design is disclosed. The method includes providing a power checker software program with one or more power checker modules that each check a particular type of power element in the ASIC design. A power checker database is created that stores the following: individual power elements in the ASIC design, a connectivity graph of the power elements, and location bins corresponding to physical areas in ASIC design that identify the power elements that are located within each area. The method further includes providing a user with a choice of which power elements in the design to check, and executing the power checker modules corresponding to the selected power elements in order to check for errors in the selected power elements. Finally, any detected errors are output for the user.
摘要翻译：公开了一种用于检查ASIC设计中的功率误差的方法。该方法包括向功率检验器软件程序提供一个或多个功率检验器模块，每个检查器模块检查ASIC设计中的特定类型的功率元件。创建一个电源检查器数据库，其存储以下内容：ASIC设计中的各个功率元件，功率元件的连接图以及对应于ASIC设计中的物理区域的位置盒，其识别位于每个区域内的功率元件。该方法还包括向用户提供选择设计中的哪些功率元件进行检查，以及执行与所选功率元件相对应的功率检验器模块，以便检查所选功率元件中的错误。最后，为用户输出任何检测到的错误。

3. 发明授权

US06560761B1 Method of datapath cell placement for bitwise and non-bitwise integrated circuit designs 有权
标题翻译：用于按位和非位元集成电路设计的数据路径单元布局方法
公开(公告)号：US06560761B1
公开(公告)日：2003-05-06
申请号：US09823184
申请日：2001-03-29
申请人： Qiong J. Yu , Alexander Tetelbuam
发明人： Qiong J. Yu , Alexander Tetelbuam
IPC分类号： G06F945
CPC分类号： G06F17/5072
摘要： A method of datapath cell placement is disclosed that minimizes signal propagation time through a datapath macro and datapath macro area that includes the steps of receiving as input a datapath description for a datapath block wherein the datapath description describes at least one of a plurality of datapath cells, a plurality of data input pins, a plurality of data output pins, and a plurality of control signal pins; sorting the plurality of data input pins and the plurality of data output pins according to a hierarchy of sorting criteria; determining a plurality of corresponding criticality values for the plurality of datapath cells; sorting the plurality of datapath cells according to the plurality of corresponding criticality values; assigning the plurality of datapath cells to a plurality of corresponding columns; and arranging the plurality of datapath cells within at least one of the plurality of corresponding columns to minimize signal propagation delay through the datapath block.
摘要翻译：公开了一种数据通路单元布置的方法，其通过数据路径宏和数据路径宏区域最小化信号传播时间，其包括以下步骤：接收数据路径块的数据路径描述作为输入，其中数据路径描述描述多个数据路径单元，多个数据输入引脚，多个数据输出引脚和多个控制信号引脚; 根据分类标准的层次对多个数据输入引脚和多个数据输出引脚进行排序; 确定所述多个数据路径小区的多个对应的临界值; 根据所述多个相应的临界值对所述多个数据通路单元进行排序; 将所述多个数据路径单元分配给多个对应的列; 以及将所述多个数据路径单元布置在所述多个对应列中的至少一个中，以使通过所述数据路径块的信号传播延迟最小化。

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