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    • 4. 发明申请
    • Power control feedback loop for adjusting a magnitude of an output signal
    • 功率控制反馈回路,用于调整输出信号的幅度
    • US20070206523A1
    • 2007-09-06
    • US11238986
    • 2005-09-30
    • Phuong HuynhNitin Sharma
    • Phuong HuynhNitin Sharma
    • H04B7/185
    • H03G3/3042H03G3/001
    • A circuit for adjusting a magnitude of a transmit signal includes a transmitter (105), providing a transmit signal (107). It also includes a transmitter amplifier (109), receiving the transmit signal (107) and a power control adjustment signal (121), and responsive thereto, providing an amplified transmit signal (111). The circuit also includes a detector (1 23), for detecting an amplitude of the amplified transmit signal (111). Also included is an error component (137) for determining the difference between the amplitude and a reference level (129). Further provided is a digital signal generator (155), receiving the difference (145), and responsive thereto, generating (157) a reference signal (125) and the power control adjustment signal (117, 121), where the reference level (129) is responsive to the reference signal (125).
    • 用于调整发射信号幅度的电路包括发射机(105),提供发射信号(107)。 它还包括发射放大器(109),接收发射信号(107)和功率控制调整信号(121),并响应于此,提供放大的发射信号(111)。 电路还包括用于检测放大的发射信号(111)的振幅的检测器(123)。 还包括用于确定幅度和参考水平(129)之间的差的误差分量(137)。 还提供了一种数字信号发生器(155),其接收差值(145),并响应于此产生(157)参考信号(125)和功率控制调节信号(117,121),其中参考电平(129 )响应于参考信号(125)。
    • 8. 发明授权
    • Bandpass-sampling delta-sigma demodulator
    • 带通采样δ-sigma解调器
    • US08717212B2
    • 2014-05-06
    • US13623350
    • 2012-09-20
    • Phuong Huynh
    • Phuong Huynh
    • H03M3/00
    • H03M3/02H03M3/40H03M3/41
    • An improved quadrature bandpass-sampling delta-sigma analog-to-digital demodulator is provided, which includes a loop filter, an A/D responsive to the loop filter, and a first feedback D/A responsive to the A/D up-converted in frequency by a first multiplier and a clock. A first summing circuit is responsive to the first D/A and an RF input for providing an input to the loop filter. A plurality of feedback D/As is responsive to the A/D up-converted in different frequencies by a plurality of multipliers and a plurality of clocks for providing feedback inputs to the loop filter. The loop filter comprises a plurality of resonators arranged in cascade configuration, a plurality of analog mixers to provide frequency shifting of the error signals propagating through the resonators, and a plurality of summing circuits responsive to the feedback D/As.
    • 提供了改进的正交带通采样Δ-Σ模数转换器,其包括环路滤波器,响应于环路滤波器的A / D和响应于A / D上变频的第一反馈D / A 频率乘第一乘法器和时钟。 第一求和电路响应于第一D / A和RF输入,用于向环路滤波器提供输入。 多个反馈D / AA响应于通过多个乘法器在不同频率中上变频的A / D和用于向环路滤波器提供反馈输入的多个时钟。 环路滤波器包括以级联配置布置的多个谐振器,多个模拟混频器,用于提供通过谐振器传播的误差信号的频移,以及响应于反馈D / A的多个求和电路。
    • 10. 发明申请
    • Quadrature bandpass-sampling delta-sigma communication receiver
    • 正交带通采样Δ-Σ通信接收机
    • US20080025437A1
    • 2008-01-31
    • US11495683
    • 2006-07-31
    • Phuong Huynh
    • Phuong Huynh
    • H04L27/00H04L27/22
    • H04L27/3881H03M3/40H03M3/424H03M3/47
    • A quadrature bandpass-sampling analog-to-digital demodulator (QBS-ADD) is provided. A radio frequency (RF) signal is received by a junction summer, which subtracts an in-phase feedback signal and a quadrature feedback signal from the RF signal to produce an error signal. The error signal is then bandpassed and amplified by the RF bandpass filter/amplifier. The amplified signal is bandpass-sampled by two low-resolution analog-to-digital converters clocking in quadrature, and is demodulated and converted into a digital in-phase signal and a digital quadrature signal. The down converted in-phase and quadrature signals are multiplied with two quadrature clocks. The results are converted to two analog signals and fed back to the RF input at the junction summer.
    • 提供了一个正交带通采样模数和数字解调器(QBS-ADD)。 射频(RF)信号通过结点加法器接收,其从RF信号中减去同相反馈信号和正交反馈信号以产生误差信号。 然后误差信号被带通并被RF带通滤波器/放大器放大。 放大的信号由正交时钟的两个低分辨率模数转换器进行带通采样,并被解调并转换为数字同相信号和数字正交信号。 下变频同相和正交信号乘以两个正交时钟。 结果转换为两个模拟信号,并在夏季结束时反馈到RF输入。