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1. 发明授权

US07517768B2 Method for fabricating a heterojunction bipolar transistor 有权
标题翻译：异质结双极晶体管的制造方法
公开(公告)号：US07517768B2
公开(公告)日：2009-04-14
申请号：US10404781
申请日：2003-03-31
申请人： Ravindra Soman , Anand Murthy , Peter VanDerVoorn , Shahriar Ahmed
发明人： Ravindra Soman , Anand Murthy , Peter VanDerVoorn , Shahriar Ahmed
IPC分类号： H01L21/331
CPC分类号： H01L29/66242
摘要： A bipolar transistor with a SiGe:C film and a seed layer forming beneath the SiGe:C film and methods of making same. The method includes placing a substrate in a reactor chamber and introducing a silicon source gas into the reactor chamber to form a silicon seed layer. The reactor chamber is maintained at a pressure below 45 Torr and a temperature between about 700° C. and 850° C. After the seed layer is formed, the silicon source gas is stopped. The reactor chamber is then simultaneously adjusted to a pressure between about 70 Torr and 90 Torr and a temperature between about 600° C. and 650° C. The silicon source gas, a germanium source gas, and a carbon source gas are introduced to form the SiGe:C film on the seed layer.
摘要翻译：具有SiGe：C膜的双极晶体管和形成在SiGe：C薄膜下面的晶种层及其制造方法。该方法包括将基板放置在反应器室中并将硅源气体引入反应器室以形成硅籽晶层。反应室保持在低于45托的压力和约700℃至850℃之间的温度。形成种子层之后，停止硅源气体。然后将反应器室同时调节至约70托和90托之间的压力以及约600℃和650℃之间的温度。引入硅源气体，锗源气体和碳源气体以形成种子层上的SiGe：C膜。

2. 发明申请

US20050266654A1 Barrier to amorphization implant 审中-公开
标题翻译：阻挡非晶化植入物
公开(公告)号：US20050266654A1
公开(公告)日：2005-12-01
申请号：US10856283
申请日：2004-05-27
申请人： Michael Hattendorf , Peter Vandervoorn
发明人： Michael Hattendorf , Peter Vandervoorn
IPC分类号： H01L21/76 , H01L21/8238
CPC分类号： H01L21/823814 , H01L21/823878
摘要： A method includes forming a first and a second semiconductor region which are joined at a semiconductor junction. The first and second semiconductor regions are truncated with an isolation trench, with an end of the semiconductor junction being disposed at the isolation trench. The isolation trench is at least partially filled with an insulation material. A salicide-blocking barrier is formed over a first surface portion of the first semiconductor region proximally disposed relative to the isolation trench. An amorphization implant is implanted in a second surface portion of the first semiconductor region distally disposed relative to the isolation trench. A salicide layer is formed in the amorphization implant.
摘要翻译：一种方法包括形成在半导体结处接合的第一和第二半导体区域。第一和第二半导体区域被隔离沟槽截短，半导体结的一端设置在隔离沟槽处。绝缘沟槽至少部分地被绝缘材料填充。在相对于隔离沟槽近端设置的第一半导体区域的第一表面部分上形成自对准阻挡屏障。非晶化注入植入在相对于隔离沟槽远离放置的第一半导体区域的第二表面部分中。在非晶化植入物中形成自对准硅化物层。

3. 发明申请

US20060148150A1 Tailoring channel dopant profiles 审中-公开
标题翻译：裁剪通道掺杂剂轮廓
公开(公告)号：US20060148150A1
公开(公告)日：2006-07-06
申请号：US11028167
申请日：2005-01-03
申请人： Jack Kavalieros , Peter Vandervoorn , Kelin Kuhn , Justin Brask , Mark Doczy , Matthew Metz , Suman Datta , Robert Chau
发明人： Jack Kavalieros , Peter Vandervoorn , Kelin Kuhn , Justin Brask , Mark Doczy , Matthew Metz , Suman Datta , Robert Chau
IPC分类号： H01L29/15 , H01L31/0312 , H01L21/336 , H01L21/8234
CPC分类号： H01L29/66537 , H01L21/823807 , H01L21/823842 , H01L29/66545
摘要： Higher mobility transistors may be achieved by removing a dummy metal gate electrode as part of a replacement metal gate process and doping the exposed channel region after source and drains have already been formed. As a result, a retrograde doping profile may be achieved in some embodiments in the channel region which is not adversely affected by subsequent high temperature processing. For example, after already forming the source and drains and thereafter doping the channel, temperature regimes greater than 900° C. may be avoided.
摘要翻译：可以通过去除虚设金属栅电极作为替代金属栅极工艺的一部分并且在源极和漏极已经形成之后掺杂暴露的沟道区域来实现更高迁移率的晶体管。结果，在一些实施例中可以在沟道区域中实现逆向掺杂分布，其不受后续高温处理的不利影响。例如，在已经形成源极并且排出并且之后掺杂通道之后，可以避免大于900℃的温度方案。

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