专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US06434433B1 External components for a microprocessor system for control of plural control elements and operating method 有权
标题翻译：用于控制多个控制元件的微处理器系统的外部组件和操作方法
公开(公告)号：US06434433B1
公开(公告)日：2002-08-13
申请号：US09346595
申请日：1999-07-02
申请人： Werner Fischer , Peter Grosshans , Mathias Kugel
发明人： Werner Fischer , Peter Grosshans , Mathias Kugel
IPC分类号： G05B1101
CPC分类号： G05B19/0423
摘要： The external intelligent component (3) connected with a microprocessor system (2) is described for essentially automatic control of a control element (1) without burdening the microprocessor system operation. The control parameters for the control element (1) are written into a data memory (6) of the external component (3) from the microprocessor system (2) and are read out internally from the data memory (6) during normal operation of the external component (3). Control of the external component (3) is possible by the microprocessor system (2) without blocking the system bus (5,7) of the microprocessor system (2) using a control line from the microprocessor to a reset input (RESET) of a controller (13) of the external component (3).
摘要翻译：描述了与微处理器系统（2）连接的外部智能组件（3），用于基本上自动控制控制元件（1），而不会对微处理器系统操作造成负担。控制元件（1）的控制参数从微处理器系统（2）写入外部部件（3）的数据存储器（6）中，并且在正常操作期间从数据存储器（6）读出外部组件（3）。使用从微处理器到复位输入（RESET）的控制线，微处理器系统（2）可以控制微处理器系统（2）的外部部件（3），而不会阻塞微处理器系统（2）的系统总线（5,7）外部组件（3）的控制器（13）。

2. 发明授权

US5898620A Method for detecting erroneously programmed memory cells in a memory 失效
标题翻译：用于检测存储器中错误编程的存储器单元的方法
公开(公告)号：US5898620A
公开(公告)日：1999-04-27
申请号：US120859
申请日：1998-07-22
申请人： Peter Grosshans
发明人： Peter Grosshans
IPC分类号： G11C16/02 , G11C16/34 , G11C29/12 , G11C29/50 , G11C29/52 , G11C16/04 , G11C7/00
CPC分类号： G11C29/52 , G06F2201/81
摘要： A method for detecting erroneously programmed memory cells of a memory, in particular for detecting overprogrammed memory cells of a flash semiconductor memory. The memory includes a plurality of memory cells, which can be subdivided into a number of blocks that can be erased as a unit, which in turn can be divided into a group of subblocks that can be programmed as a unit. The erroneous programming of a memory cell of a subblock causes each subblock of a number of subblocks that can be represented by an erroneously programmed subgroup to have a similarly erroneously programmed memory cell.
摘要翻译：一种用于检测存储器的错误编程存储单元的方法，特别是用于检测闪存半导体存储器的过程编程存储单元。存储器包括多个存储器单元，其可以被细分为可作为一个单元擦除的多个块，而这些块又可以被划分成可被编程为一个单元的一组子块。子块的存储器单元的错误编程使得可以由错误编程的子组表示的多个子块的每个子块具有类似的错误编程的存储器单元。

3. 发明授权

US06480910B1 Digital interface unit with selective input registers providing control values to output registers that simultaneously output the control values when activated by control line 失效
标题翻译：数字接口单元，具有选择性输入寄存器，为控制线激活时同时输出控制值的输出寄存器提供控制值
公开(公告)号：US06480910B1
公开(公告)日：2002-11-12
申请号：US09346596
申请日：1999-07-02
申请人： Werner Fischer , Peter Grosshans , Mathias Kugel
发明人： Werner Fischer , Peter Grosshans , Mathias Kugel
IPC分类号： G06F300
CPC分类号： G06F5/06
摘要： The digital interface unit (1) for control of a peripheral device, especially for controlling a magnetic valve for an injection device, includes a plurality of output registers (2 to 5), which store and output a set of control variables applied to the input sides of the respective output registers in response to a control signal (18, MST E). So that the control variables are output from the output registers exactly simultaneously even though they are received sequentially, at least one group of buffer registers (12 to 15, 24 to 27) is connected to the output registers (2 to 5). The buffer register or registers provides intermediate storage for the control variables prior to output from the interface unit.
摘要翻译：用于控制外围设备的数字接口单元（1），特别是用于控制用于注射装置的电磁阀，包括多个输出寄存器（2至5），其输出施加到输入端的一组控制变量响应于控制信号（18，MST E）的各个输出寄存器的侧面。因此，即使顺序地接收控制变量，也可以从输出寄存器输出控制变量，至少有一组缓冲寄存器（12〜15,24〜27）与输出寄存器（2〜5）连接。在从接口单元输出之前，缓冲寄存器或寄存器为控制变量提供中间存储。

4. 发明授权

US4754222A Method for detecting and evaluating dropouts in recording media having digital signals recorded thereon 失效
标题翻译：用于检测和评估其上记录有数字信号的记录介质中的丢失的方法
公开(公告)号：US4754222A
公开(公告)日：1988-06-28
申请号：US947178
申请日：1986-12-29
申请人： Peter Felleisen , Aribert Krug , Peter Grosshans
发明人： Peter Felleisen , Aribert Krug , Peter Grosshans
IPC分类号： G01R33/12 , G11B5/00 , G11B5/09 , G11B5/84 , G11B20/10 , G11B20/18 , G11B27/36
CPC分类号： G11B20/10009 , G11B20/18
摘要： A method and circuit arrangements for detecting and evaluating dropouts or drop-ins on recording media, comprising reading and modifying the recorded digital signals, the size and type of fault being evaluated on the basis of fixed threshold levels. In the case of a dropout, for example, the fault is weighted by determining the differential of the envelope of the read signal. In the case of a drop-in, other noise signals are left out of consideration by nonlinear emphasis of the drop-in and appropriate choice of the threshold value. A circuit combination enables both dropouts and drop-ins to be detected and evaluated.
摘要翻译：一种用于检测和评估记录介质上的丢失或丢弃的方法和电路装置，包括基于固定的阈值水平读取和修改所记录的数字信号，所评估的故障的大小和类型。例如，在丢失的情况下，通过确定读取信号的包络的差分来对故障进行加权。在插入的情况下，通过非常强调插入和适当选择阈值来考虑其他噪声信号。电路组合使得能够检测和评估掉落和掉落。

5. 发明授权

US6161190A Clock signal loading device and method 失效
标题翻译：时钟信号加载装置及方法
公开(公告)号：US6161190A
公开(公告)日：2000-12-12
申请号：US84829
申请日：1998-05-26
申请人： Werner Fischer , Peter Grosshans , Kai-Lars Barbehoen
发明人： Werner Fischer , Peter Grosshans , Kai-Lars Barbehoen
IPC分类号： B60R16/02 , B60R16/03 , G06F1/04 , G06F1/06 , G06F1/08
CPC分类号： G06F1/04 , B60R16/0315
摘要： A clock signal loading device for a processor of a controller connected to a network and a clock signal loading method are provided. The device includes a first oscillator for generating a clock signal that can be loaded to the processor, a controllable clock signal changer for changing the clock signal generated by the first oscillator, and a control device connected to the network for generating a control signal for controlling the clock signal changer as a function of the communication signals transmitted over the network. This device and method allows the frequency of the clock signal needed by the processor to be tuned in a simple and flexible manner.
摘要翻译：提供了一种用于连接到网络的控制器的处理器的时钟信号加载装置和时钟信号加载方法。该装置包括用于产生可加载到处理器的时钟信号的第一振荡器，用于改变由第一振荡器产生的时钟信号的可控时钟信号变换器，以及连接到网络的控制装置，用于产生用于控制的控制信号时钟信号变换器作为通过网络发送的通信信号的函数。该设备和方法允许以简单和灵活的方式调整处理器所需的时钟信号的频率。

6. 发明授权

US4656420A Method and circuit arrangements for detecting and evaluating faults in recording media having digital signals recorded on one or more tracks 失效
标题翻译：用于检测和评估具有记录在一个或多个轨道上的数字信号的记录介质中的故障的方法和电路装置
公开(公告)号：US4656420A
公开(公告)日：1987-04-07
申请号：US540385
申请日：1983-10-11
申请人： Peter Felleisen , Aribert Krug , Peter Grosshans
发明人： Peter Felleisen , Aribert Krug , Peter Grosshans
IPC分类号： G01R33/12 , G11B5/00 , G11B5/09 , G11B5/84 , G11B20/10 , G11B20/18 , G11B27/36
CPC分类号： G11B20/10009 , G11B20/18
摘要： A method and circuit arrangements for detecting and evaluating dropouts or drop-ins on recording media, comprising reading and modifying the recorded digital signals, the size and type of fault being evaluated on the basis of fixed threshold levels. In the case of a dropout, for example, the fault is weighted by determining the differential of the envelope of the read signal. In the case of a drop-in, other noise signals are left out of consideration by nonlinear emphasis of the drop-in and appropriate choice of the threshold value. A circuit combination enables both dropouts and drop-ins to be detected and evaluated.
摘要翻译：一种用于检测和评估记录介质上的丢失或丢弃的方法和电路装置，包括基于固定的阈值水平读取和修改所记录的数字信号，所评估的故障的大小和类型。例如，在丢失的情况下，通过确定读取信号的包络的差分来对故障进行加权。在插入的情况下，通过非常强调插入和适当选择阈值来考虑其他噪声信号。电路组合使得能够检测和评估掉落和掉落。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式