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1. 发明授权

US08397005B2 Masked register write method and apparatus 有权
标题翻译：屏蔽寄存器写入方法和装置
公开(公告)号：US08397005B2
公开(公告)日：2013-03-12
申请号：US12724932
申请日：2010-03-16
申请人： Rickard Andersson , Karl Komierowski , Ulf Morland , Per-Inge Tallberg
发明人： Rickard Andersson , Karl Komierowski , Ulf Morland , Per-Inge Tallberg
IPC分类号： G06F12/02
CPC分类号： G06F13/385
摘要： A hardware device register is written without transferring the register content from the hardware device to a host device over an interface bus for modification. The hardware device receives an address identifying the target register included in the hardware device and bit information associated with a write operation involving the target register from the host device over the interface bus. The address is stored in a first register included in the hardware device and dedicated for supporting write operations. The bit information is stored in a second register included in the hardware device and also dedicated for supporting write operations. The target register is accessed based on the address stored in the first register dedicated for supporting write operations and one or more bits of the target register are written based on the bit information without first transferring the register content to the host device over the interface bus.
摘要翻译：写入硬件设备寄存器，而不通过接口总线将硬件设备的寄存器内容传送到主机设备进行修改。硬件设备通过接口总线从主机设备接收标识包括在硬件设备中的目标寄存器的地址和与涉及目标寄存器的写入操作相关联的位信息。该地址存储在包括在硬件设备中的专用于支持写入操作的第一寄存器中。位信息存储在包括在硬件设备中的第二寄存器中，并且还专用于支持写入操作。基于存储在专用于支持写入操作的第一寄存器中的地址来访问目标寄存器，并且基于位信息写入目标寄存器的一个或多个位，而无需通过接口总线将寄存器内容传送到主机设备。

2. 发明申请

US20110213906A1 Interrupt Controller and Methods of Operation 有权
标题翻译：中断控制器和操作方法
公开(公告)号：US20110213906A1
公开(公告)日：2011-09-01
申请号：US13063674
申请日：2009-08-28
申请人： Harald Gustafsson , Ulf Morland , Per-Inge Tallberg
发明人： Harald Gustafsson , Ulf Morland , Per-Inge Tallberg
IPC分类号： G06F13/24
CPC分类号： G06F13/24 , Y02D10/14
摘要： Methods of operation and interrupt controllers for generating interrupt signals to a unit, which could enter an active mode and a non-active mode, are disclosed. The interrupt controllers have interrupt logic (204) adapted for receiving requests for interrupt, activity mode logic (202) adapted for receiving information whether the unit is in non-active mode, and delay control logic (203) adapted for delaying the interrupt to the unit when the received information indicates that the unit is in non-active mode.
摘要翻译：公开了用于向可能进入活动模式和非活动模式的单元产生中断信号的操作方法和中断控制器。所述中断控制器具有适于接收中断请求的中断逻辑（204），适于接收关于所述单元处于非活动模式的信息的活动模式逻辑（202）以及适于将所述中断延迟到所述中断的延迟控制逻辑当接收到的信息表示本机处于非活动模式时，单位为单位。

3. 发明申请

US20110231587A1 Masked Register Write Method and Apparatus 有权
标题翻译：屏蔽寄存器写入方法和装置
公开(公告)号：US20110231587A1
公开(公告)日：2011-09-22
申请号：US12724932
申请日：2010-03-16
申请人： Rickard Andersson , Karl Komierowski , Ulf Morland , Per-Inge Tallberg
发明人： Rickard Andersson , Karl Komierowski , Ulf Morland , Per-Inge Tallberg
IPC分类号： G06F12/02 , G06F13/20
CPC分类号： G06F13/385
摘要： A hardware device register is written without transferring the register content from the hardware device to a host device over an interface bus for modification. The hardware device receives an address identifying the target register included in the hardware device and bit information associated with a write operation involving the target register from the host device over the interface bus. The address is stored in a first register included in the hardware device and dedicated for supporting write operations. The bit information is stored in a second register included in the hardware device and also dedicated for supporting write operations. The target register is accessed based on the address stored in the first register dedicated for supporting write operations and one or more bits of the target register are written based on the bit information without first transferring the register content to the host device over the interface bus.
摘要翻译：写入硬件设备寄存器，而不通过接口总线将硬件设备的寄存器内容传送到主机设备进行修改。硬件设备通过接口总线从主机设备接收标识包括在硬件设备中的目标寄存器的地址和与涉及目标寄存器的写入操作相关联的位信息。该地址存储在包括在硬件设备中的专用于支持写入操作的第一寄存器中。位信息存储在包括在硬件设备中的第二寄存器中，并且还专用于支持写入操作。基于存储在专用于支持写入操作的第一寄存器中的地址来访问目标寄存器，并且基于位信息写入目标寄存器的一个或多个位，而无需通过接口总线将寄存器内容传送到主机设备。

4. 发明授权

US08566493B2 Interrupt controller and methods of operation 有权
标题翻译：中断控制器和操作方法
公开(公告)号：US08566493B2
公开(公告)日：2013-10-22
申请号：US13063674
申请日：2009-08-28
申请人： Harald Gustafsson , Ulf Morland , Per-Inge Tallberg
发明人： Harald Gustafsson , Ulf Morland , Per-Inge Tallberg
IPC分类号： G06F13/24
CPC分类号： G06F13/24 , Y02D10/14
摘要： Methods of operation and interrupt controllers for generating interrupt signals to a unit, which could enter an active mode and a non-active mode, are disclosed. The interrupt controllers have interrupt logic (204) adapted for receiving requests for interrupt, activity mode logic (202) adapted for receiving information whether the unit is in non-active mode, and delay control logic (203) adapted for delaying the interrupt to the unit when the received information indicates that the unit is in non-active mode.
摘要翻译：公开了用于向可能进入活动模式和非活动模式的单元产生中断信号的操作方法和中断控制器。所述中断控制器具有适于接收中断请求的中断逻辑（204），适于接收关于所述单元处于非活动模式的信息的活动模式逻辑（202）以及适于将所述中断延迟到所述中断的延迟控制逻辑当接收到的信息表示本机处于非活动模式时，单位为单位。

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