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1. 发明授权

US08450157B2 Methods of manufacturing master, pixel array substrate and electro-optical device 有权
标题翻译：制造主像素阵列基板和电光器件的方法
公开(公告)号：US08450157B2
公开(公告)日：2013-05-28
申请号：US13338242
申请日：2011-12-28
申请人： Pei-Ming Chen , Chih-Hung Shih
发明人： Pei-Ming Chen , Chih-Hung Shih
IPC分类号： H01L23/60
CPC分类号： H01L27/0248
摘要： A master having a substrate including displaying units and an ESD protection structure including an adjacent first region and a second region is provided. The displaying units have a predetermined-cutting region therebetween. Each displaying unit includes a peripheral circuit region and a display region having pixels. The ESD protection structure disposed on the predetermined-cutting region, located in the peripheral circuit region, and connecting the display region includes a first patterned conductive layer disposed on the first region and having an end away from the predetermined-cutting region, a first patterned dielectric layer disposed on the first patterned conductive layer and the substrate and having a first opening exposing a portion of the first patterned conductive layer, a patterned transparent conductive layer disposed corresponding to the predetermined-cutting region and connecting the first patterned conductive layer, and a second patterned dielectric layer covering the patterned transparent conductive layer and the substrate.
摘要翻译：提供具有包括显示单元的基板和包括相邻的第一区域和第二区域的ESD保护结构的主板。显示单元之间具有预定切割区域。每个显示单元包括外围电路区域和具有像素的显示区域。设置在预定切割区域上的ESD保护结构，位于外围电路区域中并连接显示区域包括设置在第一区域上并且具有远离预定切割区域的端部的第一图案化导电层，第一图案化电介质层，设置在第一图案化导电层和基板上，并具有暴露第一图案化导电层的一部分的第一开口，对应于预定切割区域设置并连接第一图案化导电层的图案化透明导电层，以及覆盖图案化的透明导电层和衬底的第二图案化介电层。

2. 发明授权

US08134210B2 Master, pixel array substrate, electro-optical device and methods of manufacturing the same 有权
标题翻译：主像素阵列基板，电光器件及其制造方法
公开(公告)号：US08134210B2
公开(公告)日：2012-03-13
申请号：US12035445
申请日：2008-02-22
申请人： Pei-Ming Chen , Chih-Hung Shih
发明人： Pei-Ming Chen , Chih-Hung Shih
IPC分类号： H01L23/60
CPC分类号： H01L27/0248
摘要： A master having a substrate including displaying units and an ESD protection structure including an adjacent first region and a second region is provided. The displaying units have a predetermined-cutting region therebetween. Each displaying unit includes a peripheral circuit region and a display region having pixels. The ESD protection structure disposed on the predetermined-cutting region, located in the peripheral circuit region, and connecting the display region includes a first patterned conductive layer disposed on the first region and having an end away from the predetermined-cutting region, a first patterned dielectric layer disposed on the first patterned conductive layer and the substrate and having a first opening exposing a portion of the first patterned conductive layer, a patterned transparent conductive layer disposed corresponding to the predetermined-cutting region and connecting the first patterned conductive layer, and a second patterned dielectric layer covering the patterned transparent conductive layer and the substrate.
摘要翻译：提供具有包括显示单元的基板和包括相邻的第一区域和第二区域的ESD保护结构的主板。显示单元之间具有预定切割区域。每个显示单元包括外围电路区域和具有像素的显示区域。设置在预定切割区域上的ESD保护结构，位于外围电路区域中并连接显示区域包括设置在第一区域上并且具有远离预定切割区域的端部的第一图案化导电层，第一图案化电介质层，设置在第一图案化导电层和基板上，并具有暴露第一图案化导电层的一部分的第一开口，对应于预定切割区域设置并连接第一图案化导电层的图案化透明导电层，以及覆盖图案化的透明导电层和衬底的第二图案化介电层。

3. 发明授权

US07969642B2 Electrophoresis display panel 有权
标题翻译：电泳显示面板
公开(公告)号：US07969642B2
公开(公告)日：2011-06-28
申请号：US12699835
申请日：2010-02-03
申请人： Chuan-Sheng Wei , Sheng-Wen Huang , Pei-Ming Chen , Chun-Hsiun Chen , Wei-Ming Huang
发明人： Chuan-Sheng Wei , Sheng-Wen Huang , Pei-Ming Chen , Chun-Hsiun Chen , Wei-Ming Huang
IPC分类号： G02B26/00
CPC分类号： G02F1/167 , G02F1/1362 , G02F2001/1672
摘要： An electrophoresis display panel including an active device array substrate and an electrophoresis display film is provided. The active device array substrate includes a plurality of active devices and a shielding pattern. The electrophoresis display film is disposed on the active device array substrate. The electrophoresis display film includes a conductive layer, a dielectric layer and a plurality of electrophoresis display mediums. The dielectric layer is disposed on the conductive layer and has a plurality of micro-cups arranged in area array. The dielectric layer is between the conductive layer and the active device array substrate. Light passing through the dielectric layer is prevented from irradiating onto the active devices by the shielding pattern. In addition, the electrophoresis display mediums are filled within the micro-cups, respectively.
摘要翻译：提供了包括有源器件阵列基板和电泳显示膜的电泳显示面板。有源器件阵列衬底包括多个有源器件和屏蔽图案。电泳显示膜配置在有源器件阵列基板上。电泳显示膜包括导电层，电介质层和多个电泳显示介质。电介质层设置在导电层上，并具有以阵列排列的多个微型杯。电介质层位于导电层和有源器件阵列衬底之间。防止穿过电介质层的光通过屏蔽图案照射到有源器件上。此外，电泳显示介质分别填充在微型杯内。

4. 发明申请

US20110141086A1 ELECTROPHORETIC DISPLAY AND METHOD OF DRIVING THE SAME 有权
标题翻译：电泳显示器及其驱动方法
公开(公告)号：US20110141086A1
公开(公告)日：2011-06-16
申请号：US12775443
申请日：2010-05-06
申请人： Chang-Yu Huang , Chuan-Sheng Wei , Pei-Ming Chen , Chun-Hsiun Chen , Wei-Ming Huang
发明人： Chang-Yu Huang , Chuan-Sheng Wei , Pei-Ming Chen , Chun-Hsiun Chen , Wei-Ming Huang
IPC分类号： G06F3/038 , G09G3/34
CPC分类号： G09G3/344 , G09G2300/08 , G09G2310/0267
摘要： An electrophoretic display with threshold voltage drift compensation functionality includes a gate driving circuit, a data driving circuit, a controller and a pixel array. The gate driving circuit provides plural gate signals according to a scan control signal. The data driving circuit provides plural data signals according to a data control signal. The controller is employed to provide the scan control signal and the data control signal. The pixel array is utilized for displaying images according to the gate signals and the data signals. Each of the gate signals includes a writing enable pulse for enabling write operations of the data signals during a writing period. And during a compensation period, each of the gate signals includes a compensation pulse for performing threshold voltage drift compensation operations on the data switches of the pixel array, and the data signals are set to hold a common voltage.
摘要翻译：具有阈值电压漂移补偿功能的电泳显示器包括栅极驱动电路，数据驱动电路，控制器和像素阵列。门驱动电路根据扫描控制信号提供多个门信号。数据驱动电路根据数据控制信号提供多个数据信号。控制器用于提供扫描控制信号和数据控制信号。像素阵列用于根据门信号和数据信号显示图像。每个门信号包括写使能脉冲，用于在写入周期期间实现数据信号的写操作。并且在补偿期间，每个门信号包括用于对像素阵列的数据开关执行阈值电压漂移补偿操作的补偿脉冲，并且数据信号被设置为保持公共电压。

5. 发明授权

US08233213B2 Electrophoresis display panel 有权
标题翻译：电泳显示面板
公开(公告)号：US08233213B2
公开(公告)日：2012-07-31
申请号：US13110003
申请日：2011-05-18
申请人： Chuan-Sheng Wei , Sheng-Wen Huang , Pei-Ming Chen , Chun-Hsiun Chen , Wei-Ming Huang
发明人： Chuan-Sheng Wei , Sheng-Wen Huang , Pei-Ming Chen , Chun-Hsiun Chen , Wei-Ming Huang
IPC分类号： G02B26/00 , G09G3/34
CPC分类号： G02F1/167 , G02F1/1362 , G02F2001/1672
摘要： An electrophoresis display panel including an active device array substrate and an electrophoresis display film is provided. The active device array substrate includes a plurality of active devices and a shielding pattern. The electrophoresis display film is disposed on the active device array substrate. The electrophoresis display film includes a conductive layer, a dielectric layer and a plurality of electrophoresis display mediums. The dielectric layer is disposed on the conductive layer and has a plurality of micro-cups arranged in area array. The dielectric layer is between the conductive layer and the active device array substrate. Light passing through the dielectric layer is prevented from irradiating onto the active devices by the shielding pattern. In addition, the electrophoresis display mediums are filled within the micro-cups, respectively.
摘要翻译：提供了包括有源器件阵列基板和电泳显示膜的电泳显示面板。有源器件阵列衬底包括多个有源器件和屏蔽图案。电泳显示膜配置在有源器件阵列基板上。电泳显示膜包括导电层，电介质层和多个电泳显示介质。电介质层设置在导电层上，并具有以阵列排列的多个微型杯。电介质层位于导电层和有源器件阵列衬底之间。防止穿过电介质层的光通过屏蔽图案照射到有源器件上。此外，电泳显示介质分别填充在微型杯内。

6. 发明授权

US08154061B2 Bottom gate thin film transistor and active array substrate 有权
标题翻译：底栅薄膜晶体管和有源阵列衬底
公开(公告)号：US08154061B2
公开(公告)日：2012-04-10
申请号：US12500609
申请日：2009-07-10
申请人： Chuan-Sheng Wei , Guang-Ren Shen , Chang-Yu Huang , Pei-Ming Chen , Sheng-Chao Liu , Chun-Hsiun Chen , Wei-Ming Huang
发明人： Chuan-Sheng Wei , Guang-Ren Shen , Chang-Yu Huang , Pei-Ming Chen , Sheng-Chao Liu , Chun-Hsiun Chen , Wei-Ming Huang
IPC分类号： H01L31/062
CPC分类号： H01L29/42384 , H01L29/41733 , H01L29/66765
摘要： A bottom gate thin film transistor and an active array substrate are provided. The bottom gate thin film transistor includes a gate, a gate insulation layer, a semiconductor layer, a plurality of sources and a plurality of drains. The gate insulation layer is disposed on the gate. The semiconductor layer is disposed on the gate insulation layer and located above the gate. An area ratio of the semiconductor layer and the gate is about 0.001 to 0.9. The sources are electrically connected with each other, and the drains are electrically connected with each other.
摘要翻译：提供底栅薄膜晶体管和有源阵列基板。底栅薄膜晶体管包括栅极，栅极绝缘层，半导体层，多个源极和多个漏极。栅极绝缘层设置在栅极上。半导体层设置在栅极绝缘层上并位于栅极上方。半导体层和栅极的面积比约为0.001〜0.9。源极彼此电连接，并且漏极彼此电连接。

7. 发明申请

US20110216394A1 ELECTROPHORESIS DISPLAY PANEL 有权
标题翻译：电子显示面板
公开(公告)号：US20110216394A1
公开(公告)日：2011-09-08
申请号：US13110003
申请日：2011-05-18
申请人： Chuan-Sheng Wei , Sheng-Wen Huang , Pei-Ming Chen , Chun-Hsiun Chen , Wei-Ming Huang
发明人： Chuan-Sheng Wei , Sheng-Wen Huang , Pei-Ming Chen , Chun-Hsiun Chen , Wei-Ming Huang
IPC分类号： G02F1/167
CPC分类号： G02F1/167 , G02F1/1362 , G02F2001/1672
摘要： An electrophoresis display panel including an active device array substrate and an electrophoresis display film is provided. The active device array substrate includes a plurality of active devices and a shielding pattern. The electrophoresis display film is disposed on the active device array substrate. The electrophoresis display film includes a conductive layer, a dielectric layer and a plurality of electrophoresis display mediums. The dielectric layer is disposed on the conductive layer and has a plurality of micro-cups arranged in area array. The dielectric layer is between the conductive layer and the active device array substrate. Light passing through the dielectric layer is prevented from irradiating onto the active devices by the shielding pattern. In addition, the electrophoresis display mediums are filled within the micro-cups, respectively.
摘要翻译：提供了包括有源器件阵列基板和电泳显示膜的电泳显示面板。有源器件阵列衬底包括多个有源器件和屏蔽图案。电泳显示膜配置在有源器件阵列基板上。电泳显示膜包括导电层，电介质层和多个电泳显示介质。电介质层设置在导电层上，并具有以阵列排列的多个微型杯。电介质层位于导电层和有源器件阵列衬底之间。防止穿过电介质层的光通过屏蔽图案照射到有源器件上。此外，电泳显示介质分别填充在微型杯内。

8. 发明申请

US20130099238A1 LIQUID CRYSTAL DISPLAY HAVING A HIGH APERTURE RATIO 审中-公开
标题翻译：具有高孔径比的液晶显示
公开(公告)号：US20130099238A1
公开(公告)日：2013-04-25
申请号：US13467047
申请日：2012-05-09
申请人： Ming-Yao Chen , Pei-Ming Chen
发明人： Ming-Yao Chen , Pei-Ming Chen
IPC分类号： H01L29/786
CPC分类号： G02F1/13471 , G02F1/1362 , H01L27/1225
摘要： A (liquid crystal display) LCD includes a pixel array and a gate driving circuit. The pixel array includes a plurality of first oxide thin film transistors, a first oxide thin film transistor of the first oxide thin film transistors with a shortest channel length having a first channel length. The gate driving circuit is coupled to the pixel array for driving the pixel array, and includes a plurality of second oxide thin film transistors. The second oxide thin film of the second oxide thin film transistors with a longest channel length has a second channel length. A ratio of the second channel length and the first channel length is greater than 1.5. By limiting the ratio of the second channel length and the first channel length, the aperture ratio of the display panel can be improved without deteriorating the operation stability of the LCD.
摘要翻译： A（液晶显示器）LCD包括像素阵列和栅极驱动电路。像素阵列包括多个第一氧化物薄膜晶体管，具有第一沟道长度的具有最短沟道长度的第一氧化物薄膜晶体管的第一氧化物薄膜晶体管。栅极驱动电路耦合到像素阵列以驱动像素阵列，并且包括多个第二氧化物薄膜晶体管。具有最长沟道长度的第二氧化物薄膜晶体管的第二氧化物薄膜具有第二沟道长度。第二通道长度与第一通道长度之比大于1.5。通过限制第二通道长度和第一通道长度的比例，可以提高显示面板的开口率，而不会降低LCD的操作稳定性。

9. 发明申请

US20120241743A1 THIN FILM TRANSISTOR 审中-公开
标题翻译：薄膜晶体管
公开(公告)号：US20120241743A1
公开(公告)日：2012-09-27
申请号：US13489458
申请日：2012-06-06
申请人： Guang-Ren Shen , Pei-Ming Chen , Chun-Hsiun Chen , Wei-Ming Huang
发明人： Guang-Ren Shen , Pei-Ming Chen , Chun-Hsiun Chen , Wei-Ming Huang
IPC分类号： H01L29/786
CPC分类号： H01L29/786
摘要： A thin film transistor (TFT) and a fabricating method thereof are provided. The TFT includes a channel layer, an ohmic contact layer, a dielectric layer, a source, a drain, a gate, and a gate insulating layer. The channel layer has an upper surface and a sidewall. The ohmic contact layer is disposed on a portion of the upper surface of the channel layer. The dielectric layer is disposed on the sidewall of the channel layer, and does not overlap with the ohmic contact layer. The source and the drain are disposed on portions of the ohmic contact layer and the dielectric layer. A portion of dielectric layer is not covered by the source or the drain. The gate is above or below the channel layer. The gate insulating layer is disposed between the gate and the channel layer.
摘要翻译：提供薄膜晶体管（TFT）及其制造方法。 TFT包括沟道层，欧姆接触层，电介质层，源极，漏极，栅极和栅极绝缘层。沟道层具有上表面和侧壁。欧姆接触层设置在沟道层的上表面的一部分上。电介质层设置在沟道层的侧壁上，并且不与欧姆接触层重叠。源极和漏极设置在欧姆接触层和电介质层的部分上。电介质层的一部分不被源极或漏极覆盖。门在通道层的上方或下方。栅极绝缘层设置在栅极和沟道层之间。

10. 发明授权

US08232147B2 Fabricating method of a thin film transistor having a dielectric layer for inhibiting leakage current 有权
标题翻译：具有用于抑制漏电流的电介质层的薄膜晶体管的制造方法
公开(公告)号：US08232147B2
公开(公告)日：2012-07-31
申请号：US12779955
申请日：2010-05-14
申请人： Guang-Ren Shen , Pei-Ming Chen , Chun-Hsiun Chen , Wei-Ming Huang
发明人： Guang-Ren Shen , Pei-Ming Chen , Chun-Hsiun Chen , Wei-Ming Huang
IPC分类号： H01L29/786
CPC分类号： H01L29/786
摘要： A thin film transistor (TFT) and a fabricating method thereof are provided. The TFT includes a channel layer, an ohmic contact layer, a dielectric layer, a source, a drain, a gate, and a gate insulating layer. The channel layer has an upper surface and a sidewall. The ohmic contact layer is disposed on a portion of the upper surface of the channel layer. The dielectric layer is disposed on the sidewall of the channel layer, and does not overlap with the ohmic contact layer. The source and the drain are disposed on portions of the ohmic contact layer and the dielectric layer. A portion of dielectric layer is not covered by the source or the drain. The gate is above or below the channel layer. The gate insulating layer is disposed between the gate and the channel layer.
摘要翻译：提供薄膜晶体管（TFT）及其制造方法。 TFT包括沟道层，欧姆接触层，电介质层，源极，漏极，栅极和栅极绝缘层。沟道层具有上表面和侧壁。欧姆接触层设置在沟道层的上表面的一部分上。电介质层设置在沟道层的侧壁上，并且不与欧姆接触层重叠。源极和漏极设置在欧姆接触层和电介质层的部分上。电介质层的一部分不被源极或漏极覆盖。门在通道层的上方或下方。栅极绝缘层设置在栅极和沟道层之间。

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