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1. 发明授权

US09007095B2 Efficient non-integral multi-height standard cell placement 有权
标题翻译：高效非积分多高度标准电池放置
公开(公告)号：US09007095B2
公开(公告)日：2015-04-14
申请号：US13467275
申请日：2012-05-09
申请人： Paul Penzes
发明人： Paul Penzes
IPC分类号： H01L25/00 , G06F17/50 , H01L27/02 , H01L27/118 , H01L23/528
CPC分类号： G06F17/5072 , H01L23/5286 , H01L27/0207 , H01L27/11807 , H01L2924/00 , H01L2924/0002
摘要： An integrated circuit including a first portion of a first cell library including a first plurality of rows, each of the first plurality of rows having a first row height and the first portion having a first portion height, a second portion of a second cell library including a second plurality of rows, each of the second plurality of rows having a second row height and the second portion having a second portion height, wherein the first portion height is equal to the second portion height and the first row height is different from the second row height, and a connector to electrically connect the first portion of the first cell library to the second portion of the second cell library.
摘要翻译：一种集成电路，包括第一单元库的第一部分，所述第一单元库包括第一多行，所述第一多行中的每一行具有第一行高度，所述第一部分具有第一部分高度，所述第二单元库的第二部分包括第二多行，第二多行中的每一行具有第二行高度，第二部分具有第二部分高度，其中第一部分高度等于第二部分高度，并且第一行高度不同于第二部分高度行高度以及将第一单元库的第一部分电连接到第二单元库的第二部分的连接器。

2. 发明申请

US20130214433A1 Efficient Non-Integral Multi-Height Standard Cell Placement 有权
标题翻译：高效的非积分多高标准细胞放置
公开(公告)号：US20130214433A1
公开(公告)日：2013-08-22
申请号：US13467275
申请日：2012-05-09
申请人： Paul Penzes
发明人： Paul Penzes
IPC分类号： H01L23/48
CPC分类号： G06F17/5072 , H01L23/5286 , H01L27/0207 , H01L27/11807 , H01L2924/00 , H01L2924/0002
摘要： An integrated circuit including a first portion of a first cell library including a first plurality of rows, each of the first plurality of rows having a first row height and the first portion having a first portion height, a second portion of a second cell library including a second plurality of rows, each of the second plurality of rows having a second row height and the second portion having a second portion height, wherein the first portion height is equal to the second portion height and the first row height is different from the second row height, and a connector to electrically connect the first portion of the first cell library to the second portion of the second cell library.
摘要翻译：一种集成电路，包括第一单元库的第一部分，所述第一单元库包括第一多行，所述第一多行中的每一行具有第一行高度，所述第一部分具有第一部分高度，所述第二单元库的第二部分包括第二多行，第二多行中的每一行具有第二行高度，第二部分具有第二部分高度，其中第一部分高度等于第二部分高度，并且第一行高度不同于第二部分高度行高度以及将第一单元库的第一部分电连接到第二单元库的第二部分的连接器。

3. 发明申请

US20130047023A1 Adaptive Clocking Scheme to Accommodate Supply Voltage Transients 有权
标题翻译：自适应时钟方案以适应电源电压瞬变
公开(公告)号：US20130047023A1
公开(公告)日：2013-02-21
申请号：US13331874
申请日：2011-12-20
申请人： Paul Penzes , Mark Fullerton
发明人： Paul Penzes , Mark Fullerton
IPC分类号： G06F1/04
CPC分类号： H03L7/0802 , G06F1/26 , G06F1/32 , G06F1/3203 , G06F1/3228 , G06F12/14 , G06F21/44 , H01L2924/0002 , H03K3/0315 , H03K3/037 , H03K3/0375 , H03K5/133 , H03K19/01 , H03K2005/00019 , H03K2005/00026 , H03K2005/00058 , H03L7/097 , H03L7/0997 , H01L2924/00
摘要： Adaptive clocking schemes for synchronized on-chip functional Hocks are provided. The clocking schemes enable synchronous clocking which can be adapted according to changes in signal path propagation delay due temperature, process, and voltage variations, for example, in embodiments, the docking schemes allow for the capacity utilization of a logic path to be increased.
摘要翻译：提供了同步片上功能Hocks的自适应时钟方案。时钟方案使得可以根据信号路径传播延迟因温度，过程和电压变化而改变的同步时钟，例如在实施例中，对接方案允许增加逻辑路径的容量利用。

4. 发明申请

US20110156749A1 High-Speed Standard Cells Designed Using a Deep-Submicron Physical Effect 有权
标题翻译：使用深亚微米物理效应设计的高速标准单元
公开(公告)号：US20110156749A1
公开(公告)日：2011-06-30
申请号：US12651109
申请日：2009-12-31
申请人： Paul Penzes
发明人： Paul Penzes
IPC分类号： H03K19/003 , H03K19/00
CPC分类号： G06F17/5068 , G06F17/505 , H01L27/0207 , H01L27/11807
摘要： A system comprises signal paths. There are first through n signal paths, n being a positive integer. A critical one of the first through n signal paths is based on being a respective one of the first through n signal paths having a slowest signal propagation and/or a path in which a signal propagates slower than a clock cycle. The critical one of the first through n signal paths comprises a first size of a standard cell including corresponding logic devices. The non-critical ones of the first through n signal paths comprise a second size of a standard cell including corresponding logic devices, the second size being smaller than the first size.
摘要翻译：系统包括信号路径。有n个信号路径，n是正整数。第一至第n信号路径中的关键因素是基于具有最慢信号传播的第一至第n信号路径中的相应一个信号传播和/或信号传播速度慢于时钟周期的路径。第一到第n个信号路径中的关键一个包括包括对应的逻辑设备的标准小区的第一大小。第一至第n信号路径中的非关键信号包括包括对应的逻辑设备的标准单元的第二大小，第二大小小于第一大小。

5. 发明授权

US09312862B2 Adaptive clocking scheme to accommodate supply voltage transients 有权
标题翻译：自适应时钟方案，以适应电源电压瞬变
公开(公告)号：US09312862B2
公开(公告)日：2016-04-12
申请号：US13331874
申请日：2011-12-20
申请人： Paul Penzes , Mark Fullerton
发明人： Paul Penzes , Mark Fullerton
IPC分类号： G06F1/04 , H03L7/08 , H03K3/03 , H03K3/037 , H03K19/01 , G06F12/14 , G06F21/44 , H03K5/13 , H03L7/097 , H03L7/099 , G06F1/32 , G06F1/26 , H03K5/00
CPC分类号： H03L7/0802 , G06F1/26 , G06F1/32 , G06F1/3203 , G06F1/3228 , G06F12/14 , G06F21/44 , H01L2924/0002 , H03K3/0315 , H03K3/037 , H03K3/0375 , H03K5/133 , H03K19/01 , H03K2005/00019 , H03K2005/00026 , H03K2005/00058 , H03L7/097 , H03L7/0997 , H01L2924/00
摘要： Adaptive clocking schemes for synchronized on-chip functional blocks are provided. The clocking schemes enable synchronous clocking which can be adapted according to changes in signal path propagation delay due temperature, process, and voltage variations, for example. In embodiments, the clocking schemes allow for the capacity utilization of a logic path to be increased.
摘要翻译：提供了同步片上功能块的自适应时钟方案。时钟方案实现了可以根据信号路径传播延迟因温度，过程和电压变化而改变的同步时钟。在实施例中，时钟方案允许增加逻辑路径的容量利用。

6. 发明申请

US20130082764A1 APPARATUS AND METHOD TO COMBINE PIN FUNCTIONALITY IN AN INTEGRATED CIRCUIT 审中-公开
标题翻译：在集成电路中组合引脚功能的装置和方法
公开(公告)号：US20130082764A1
公开(公告)日：2013-04-04
申请号：US13250677
申请日：2011-09-30
申请人： Paul Penzes , Love Kothari , Ajat Hukkoo , Mark Fullerton , Veronica Alarcon , Zhongmin Zhang , Kerry Alan Thompson , Russell Radke
发明人： Paul Penzes , Love Kothari , Ajat Hukkoo , Mark Fullerton , Veronica Alarcon , Zhongmin Zhang , Kerry Alan Thompson , Russell Radke
IPC分类号： G05F3/02 , H03B1/00 , G11C5/14
CPC分类号： G11C29/56 , G11C2029/5602
摘要： An apparatus and method are disclosed to combine pad functionality in an integrated circuit. A power, ground, or signal pad is connected to a power, ground, or signal source, respectively. The power, ground, or signal pad is additionally connected to an additional signal source, such as automatic test equipment in a testing environment. By temporarily disconnecting either the power, ground, or signal source, from the functional block within the integrated circuit to which the source is delivered, the same pad may pass in another signal to other portions of the integrated circuit. In the alternative, the same pad may pass in another signal to other portions of the integrated circuit without disconnecting the original signal by coupling the additional signal over the original signal. Further, combining pad functionality enables reuse of an input pad as an output pad for signals originating from within the integrated circuit.
摘要翻译：公开了一种在集成电路中组合焊盘功能的装置和方法。电源，接地或信号焊盘分别连接到电源，接地或信号源。电源，接地或信号焊盘另外连接到附加信号源，例如测试环境中的自动测试设备。通过将电源，接地或信号源暂时断开与源传输到的集成电路内的功能块，同一焊盘可以将另一个信号传递到集成电路的其他部分。在替代方案中，相同的焊盘可以将另一个信号传递到集成电路的其它部分，而不会通过在原始信号上耦合附加信号来断开原始信号。此外，组合焊盘功能使得可以将输入焊盘重新用作来自集成电路内的信号作为输出焊盘。

7. 发明授权

US08079008B2 High-speed low-leakage-power standard cell library 失效
标题翻译：高速低漏电标准单元库
公开(公告)号：US08079008B2
公开(公告)日：2011-12-13
申请号：US12060108
申请日：2008-03-31
申请人： Paul Penzes , Alvin Lin , Vafa James Rakshani
发明人： Paul Penzes , Alvin Lin , Vafa James Rakshani
IPC分类号： G06F17/50
CPC分类号： G06F17/5045 , G06F17/505 , G06F2217/66
摘要： A high-speed, low leakage-power Standard Cell Library is provided. The high-speed, low-leakage-power Standard Cell Library provides the extra drive-strength of a taller X-Track library (e.g., 14-Track library) and low leakage-power comparable to that of a smaller, N-Track library (e.g., 10-Track library). The high-speed, low leakage-power Standard Cell Library includes a set of cells each having a device area designed to provide maximum drive strength for the cell. The high-speed, low leakage-power Standard Cell Library further includes a second set of cells having varying device areas that provide reduced leakage power characteristics comparable to cells in the smaller, N-Track library. The modified reduced leakage-power cells are formed by adding padding to the cell to achieve a desired leakage-power characteristic of the cell.
摘要翻译：提供高速，低泄漏功率的标准单元库。高速，低漏电功率的标准单元库提供了更高的X-Track库（例如14轨道库）的额外驱动强度和与较小的N-Track库相当的低泄漏功率（例如，10轨道图书馆）。高速，低泄漏功率的标准电池库包括一组电池，每个电池都具有设计用于为电池提供最大驱动强度的器件区域。高速，低泄漏功率的标准单元库还包括具有变化的器件区域的第二组单元，其提供与较小的N-Track库中的单元相当的减小的漏电功率特性。修改后的减少漏电功率单元是通过向单元增加填充形成的，以实现单元所需的漏电功率特性。

8. 发明申请

US20080301412A1 High speed multiplexer 有权
标题翻译：高速多路复用器
公开(公告)号：US20080301412A1
公开(公告)日：2008-12-04
申请号：US11807973
申请日：2007-05-30
申请人： Paul Penzes
发明人： Paul Penzes
IPC分类号： H03K19/00 , H03K17/00
CPC分类号： H03K17/005
摘要： According to one embodiment, a high speed multiplexer includes a number of data inputs, a number of hot code select inputs, and a final data output. In one embodiment, the high speed multiplexer utilizes a number of intermediate multiplexers, each receiving respective hot code select inputs and providing an intermediate data output. In one embodiment, each intermediate multiplexer has a critical delay path comprising a first NAND gate and a second NAND gate. In one implementation a four-to-one intermediate multiplexer comprises a first two-input NAND gate and a second four-input NAND gate. In one embodiment, a 32-to-1 high speed multiplexer comprises four four-to-one intermediate multiplexers. According to one implementation of this embodiment, the 32-to-1 multiplexer has a critical delay path from any of the data inputs to the final data output comprising a first NAND gate, a second NAND gate, a NOR gate, and a third NAND gate.
摘要翻译：根据一个实施例，高速复用器包括多个数据输入，多个热代码选择输入和最终数据输出。在一个实施例中，高速多路复用器利用多个中间多路复用器，每个接收各自的热码选择输入并提供中间数据输出。在一个实施例中，每个中间多路复用器具有包括第一NAND门和第二NAND门的临界延迟路径。在一个实现中，四对一中间多路复用器包括第一双输入NAND门和第二四输入NAND门。在一个实施例中，32对1高速复用器包括四个四对一中间多路复用器。根据该实施例的一个实现方式，32对1多路复用器具有从任何数据输入到最终数据输出的关键延迟路径，包括第一NAND门，第二NAND门，NOR门和第三NAND 门。

9. 发明授权

US08700972B2 Adaptive ultra-low voltage memory 有权
标题翻译：自适应超低电压存储器
公开(公告)号：US08700972B2
公开(公告)日：2014-04-15
申请号：US13289691
申请日：2011-11-04
申请人： Paul Penzes , Mark Fullerton , Ajat Hukkoo , John Walley
发明人： Paul Penzes , Mark Fullerton , Ajat Hukkoo , John Walley
IPC分类号： H03M13/00 , G11C29/00
CPC分类号： G06F1/3275 , G06F1/3206 , G06F1/3296 , G06F11/1064 , G06F12/0864 , G06F2212/1028 , G06F2212/601 , H03M13/19 , H03M13/3715 , Y02D10/13 , Y02D10/14 , Y02D10/172
摘要： Embodiments provide an adaptive memory that allows for low voltage modes of operation. In the low voltage modes of operation, the supply voltage provided to the memory is reduced below Vcc(min), which allows for significant savings in the power consumption of circuit components (e.g., the CPU) whose minimum voltage is dictated by Vcc(min). According to further embodiments, the memory can be configured dynamically according to various configurations depending on desired power savings (e.g., target Vcc(min)) and/or performance requirements (e.g., reliability, cache size requirement, etc.).
摘要翻译：实施例提供允许低电压操作模式的自适应存储器。在低电压工作模式下，提供给存储器的电源电压降至低于Vcc（min），这样可以显着节省最小电压由Vcc（min）决定的电路组件（例如CPU）的功耗）。根据另外的实施例，可以根据期望的功率节省（例如，目标Vcc（min））和/或性能要求（例如，可靠性，高速缓存大小要求等）根据各种配置来动态地配置存储器。

10. 发明申请

US20130117626A1 Adaptive Ultra-Low Voltage Memory 有权
标题翻译：自适应超低电压存储器
公开(公告)号：US20130117626A1
公开(公告)日：2013-05-09
申请号：US13289691
申请日：2011-11-04
申请人： Paul PENZES , Mark Fullerton , Ajat Hukkoo , John Walley
发明人： Paul PENZES , Mark Fullerton , Ajat Hukkoo , John Walley
IPC分类号： H03M13/09 , G06F11/10 , G06F1/26
CPC分类号： G06F1/3275 , G06F1/3206 , G06F1/3296 , G06F11/1064 , G06F12/0864 , G06F2212/1028 , G06F2212/601 , H03M13/19 , H03M13/3715 , Y02D10/13 , Y02D10/14 , Y02D10/172
摘要： Embodiments provide an adaptive memory that allows for low voltage modes of operation. In the low voltage modes of operation, the supply voltage provided to the memory is reduced below Vcc(min), which allows for significant savings in the power consumption of circuit components (e.g., the CPU) whose minimum voltage is dictated by Vcc(min). According to further embodiments, the memory can be configured dynamically according to various configurations depending on desired power savings (e.g., target Vcc(min)) and/or performance requirements (e.g., reliability, cache size requirement, etc.).
摘要翻译：实施例提供允许低电压操作模式的自适应存储器。在低电压工作模式下，提供给存储器的电源电压降至低于Vcc（min），这样可以显着节省最小电压由Vcc（min）决定的电路组件（例如CPU）的功耗）。根据另外的实施例，可以根据期望的功率节省（例如，目标Vcc（min））和/或性能要求（例如，可靠性，高速缓存大小要求等）根据各种配置来动态地配置存储器。

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