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1. 发明授权

US5030931A Folding delay line 失效
标题翻译：折叠延时线
公开(公告)号：US5030931A
公开(公告)日：1991-07-09
申请号：US352354
申请日：1989-05-16
申请人： Mark Brooks , J. Paul Ozawa , Gary L. Seibel
发明人： Mark Brooks , J. Paul Ozawa , Gary L. Seibel
IPC分类号： H01P3/08 , H01P9/00
CPC分类号： H01P9/006
摘要： A flexible laminated delay line assembly formed to include a plurality of patterned regions which may be folded into sandwiched relation to one another without affecting electrical continuity. The transmission line layer is laminated between successively adjacent dielectric and ground plane layers. Windows cut into the ground plane and dielectric layers facilitate folding and decoupling of a support spine, folding of the conductor sections and sizing of the assembly. In one construction, the dielectric layers comprise a flexible insulative substrate laminated between upper and lower thermoset layers. In another construction the dielectric layers comprise a polyetherimide that is melt flowed about the pathways of the transmission line.
摘要翻译：柔性层压延迟线组件，其形成为包括多个图案化区域，其可以折叠成彼此夹持而不影响电连续性。传输线层层叠在连续相邻的电介质层和接地层之间。窗口切入接地平面，电介质层便于支撑脊的折叠和解耦，导体部分的折叠和组件的尺寸。在一种结构中，电介质层包括层压在上部和下部热固性层之间的柔性绝缘基底。在另一种结构中，电介质层包括聚醚酰亚胺，其在传输线的路径处熔融流动。

2. 发明授权

US4942373A Thin film delay lines having a serpentine delay path 失效
标题翻译：具有蛇形延迟路径的薄膜延迟线
公开(公告)号：US4942373A
公开(公告)日：1990-07-17
申请号：US180353
申请日：1988-04-11
申请人： Paul Ozawa , Mark Brooks , Fumitoshi Nakanata
发明人： Paul Ozawa , Mark Brooks , Fumitoshi Nakanata
IPC分类号： H01P9/00
CPC分类号： H01P9/006
摘要： Multi-layered, thick/thin film, nanosecond delay lines, the inductive/capacitive characteristics of which are tailored to provide line impedances yielding unit delays of 1 to 10 nanoseconds. The delay lines are constructed on a supporting ceramic, resin/fiber or plastic substrate. In alternative embodiments, a serpentine conductive layer of tailored line widths and conductor spacings is sandwiched relative to overlying dielectric layers of 25 to 200 microns thickness and associated ground plane layers. In another embodiment, multiple conductor layers are sandwiched relative to intervening dielectric and ground plane layers. Lateral contact pads/pins, vertical vias and jumper conductors permit circuit connection and interconnection of the layers.
摘要翻译：多层，厚/薄膜，纳秒延迟线，其电感/电容特性被定制以提供线阻抗，产生1至10纳秒的单位延迟。延迟线构造在支撑陶瓷，树脂/纤维或塑料基板上。在替代实施例中，相对于25至200微米厚度和相关联的接地平面层的覆盖电介质层夹着具有定制线宽度和导体间隔的蛇形导电层。在另一个实施例中，多个导体层相对于中间介电层和接地平面层被夹持。横向接触焊盘/引脚，垂直通孔和跳线导体允许电路连接和互连。

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