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    • 2. 发明申请
    • Interpolated timestamps in high-speed data capture and analysis
    • 在高速数据采集和分析中插补时间戳
    • US20060248106A1
    • 2006-11-02
    • US11082791
    • 2005-03-17
    • Andrew MilnePaul Gentieu
    • Andrew MilnePaul Gentieu
    • G06F17/00G06F7/00
    • H04L43/106H04L43/0847
    • Methods and apparatuses for using interpolation to associate timestamp values to data received in a data capture and analysis system. An analysis processor receives data representing data transferred in a communications link. The analysis processor also receives timestamp signals. The analysis processor performs an interpolation between at least two timestamp values received and associates results of the interpolation with the data. The analysis processor analyzes the data. A logic device can be coupled to the analysis processor to interleave timestamp signal values with the data and transmit the interleaved data and timestamp signals to the analysis processor.
    • 用于内插的方法和装置将时间戳值与在数据捕获和分析系统中接收的数据相关联。 分析处理器接收表示在通信链路中传送的数据的数据。 分析处理器还接收时间戳信号。 分析处理器在接收到的至少两个时间戳值之间执行内插,并将内插的结果与数据相关联。 分析处理器分析数据。 逻辑设备可以耦合到分析处理器,以将时间戳信号值与数据进行交织,并将交错的数据和时间戳信号发送到分析处理器。
    • 3. 发明授权
    • Bit error rate tester
    • 误码率测试仪
    • US07032139B1
    • 2006-04-18
    • US10179760
    • 2002-06-24
    • Farhad IryamiPaul Gentieu
    • Farhad IryamiPaul Gentieu
    • H03M13/01
    • H04L1/242H04L1/203
    • The present invention is a bit error rate tester that may operate on network paths having devices that add or drop idles within a transmitted bit sequence. In particular, the bit sequence determines whether a received bit sequence is synchronized. If the received sequence is not synchronized or if a certain event/threshold is reached, then the bit error rate tester re-synchronizes the sequence prior to analysis. Also, the bit error rate detector is able to operate on high-speed networks and provide bit granularity measurements.
    • 本发明是一种误码率测试器,其可以在具有在发送的比特序列内添加或丢弃空闲的设备的网络路径上操作。 特别地,比特序列确定接收的比特序列是否被同步。 如果接收到的序列不同步或者达到某个事件/阈值,则误码率测试仪在分析前重新同步序列。 此外,误码率检测器能够在高速网络上运行并提供位粒度测量。
    • 6. 发明申请
    • Diagnostics for a Serial Communications Device
    • 串行通信设备诊断
    • US20120204066A1
    • 2012-08-09
    • US13449226
    • 2012-04-17
    • Gayle Loretta Ray NoblePaul Gentieu
    • Gayle Loretta Ray NoblePaul Gentieu
    • G06F11/28
    • G06F11/0766G06F11/0745G06F13/4295G06F2213/0028G06F2213/0032H04B10/801
    • A serial communications device comprises a controller to obtain digital diagnostic data representative of operational characteristics of the serial communications device, memory to store the digital diagnostic data and at least one interface, including an interface to serially communicate data via a serial cable. The serial communications device also comprises a signal controller configured to encode the digital diagnostic data onto a serial data signal for transmission via the serial cable by adjusting signal levels of the serial data signal while preserving original data in the serial data signal. Encoding the digital diagnostic data includes serializing the digital diagnostic data, determining a series of signal levels for the serialized digital diagnostic data based on a signal encoding map, and adjusting signal levels for the serial data signal based on the determined series of signal levels.
    • 串行通信设备包括控制器,用于获得表示串行通信设备的操作特性的数字诊断数据,用于存储数字诊断数据的存储器和至少一个接口,包括经由串行电缆串行传送数据的接口。 串行通信设备还包括信号控制器,该信号控制器被配置为将数字诊断数据编码到串行数据信号上,以便通过串行数据信号的信号电平进行调整,同时保留串行数据信号中的原始数据。 编码数字诊断数据包括串行化数字诊断数据,基于信号编码图确定用于串行化数字诊断数据的一系列信号电平,以及基于所确定的一系列信号电平来调整串行数据信号的信号电平。
    • 7. 发明申请
    • NETWORK TAP/AGGREGATOR CONFIGURED FOR POWER OVER ETHERNET OPERATION
    • NETWORK TAP / AGGREGATOR被配置为以太网供电
    • US20070081549A1
    • 2007-04-12
    • US11421372
    • 2006-05-31
    • Christopher CicchettiArthur LawsonGreta LightPaul GentieuTimothy BeyersDonald Blackwell
    • Christopher CicchettiArthur LawsonGreta LightPaul GentieuTimothy BeyersDonald Blackwell
    • H04L12/413
    • H04L12/10H04L12/40032H04L12/40045H04L43/00Y02D50/30
    • A network tap device array capable of being powered by a power-over Ethernet (“POE”) supply is disclosed. The array enables data from multiple nodes in a communications network to be tapped and forwarded to a plurality of monitoring devices. In one embodiment the network tap device array includes a chassis that is configured to receive a plurality of network tap devices that are each powered by a POE supply. Each network tap device includes network ports for receiving and transmitting network data via communication cables and tap ports for forwarding the tapped network data to the monitoring device. In another embodiment, a sub-chassis includes a plurality of network tap devices and an aggregator that aggregates tapped data from each of the tap devices. The aggregator then forwards the aggregated data to the monitoring device. The sub-chassis can be included in a chassis that is configured to receive multiple populated chassis.
    • 公开了能够通过以太网供电(“POE”)供电的网络抽头设备阵列。 该阵列使来自通信网络中的多个节点的数据能够被抽头并转发到多个监视设备。 在一个实施例中,网络抽头设备阵列包括被配置为接收多个网络抽头设备的机架,每个网络抽头设备由POE供电供电。 每个网络抽头设备包括用于经由通信电缆和抽头端口接收和发送网络数据的网络端口,用于将分接的网络数据转发到监控设备。 在另一个实施例中,子机架包括多个网络抽头设备和聚合来自每个抽头设备的抽头数据的聚合器。 然后,聚合器将聚合的数据转发到监控设备。 子机箱可以包含在配置为接收多个填充机箱的机箱中。
    • 8. 发明申请
    • System and method for network error rate testing
    • 网络错误率测试的系统和方法
    • US20060200708A1
    • 2006-09-07
    • US10422456
    • 2003-04-24
    • Paul GentieuChris CicchettiArthur LawsonAn HuynhHarold Yang
    • Paul GentieuChris CicchettiArthur LawsonAn HuynhHarold Yang
    • G06F11/00
    • H04L43/50H04L1/243H04L1/244H04L43/06H04L43/0847H04L43/18
    • An bit error rate tester for use in connection with a high speed networks. The bit error rate tester includes transmit and receive ports, as well as a sequence generator, memory, synchronizer, sequence start detect module, and comparator. The sequence generator generates a bit sequence for transmission through a network path. The bit sequence returns to the bit error rate tester by way of the receive port. The synchronizer then bit-aligns the received bit sequence to compensate for idles/fill words added/dropped as the bit sequence transited the network. The synchronized bit sequence is passed to the start word detector which detects start and end words in the bit sequence and instructs the comparator to compare only data between the start and end words. The comparator compares the received bit sequence with a copy of the transmitted bit sequence regenerated from the memory, and calculates a bit error rate.
    • 用于与高速网络连接的误码率测试仪。 误码率测试仪包括发送和接收端口,以及序列发生器,存储器,同步器,序列启动检测模块和比较器。 序列生成器生成用于通过网络路径传输的比特序列。 位序列通过接收端口返回到误码率测试仪。 然后,同步器对接收到的比特序列进行比特对齐,以补偿随着网络中的比特序列的添加/删除。 同步位序列被传送到起始字检测器,其检测位序列中的起始字和结束字,并指示比较器仅比较起始字和结束字之间的数据。 比较器将接收到的比特序列与从存储器再生的发送比特序列的副本进行比较,并计算比特错误率。