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1. 发明授权

US07607031B2 Power management in a communication link 有权
标题翻译：通信链路中的电源管理
公开(公告)号：US07607031B2
公开(公告)日：2009-10-20
申请号：US11482269
申请日：2006-07-07
申请人： Paul A. Mackey , Paul C. Miranda , Larry D. Hewitt , Jonathan M. Owen
发明人： Paul A. Mackey , Paul C. Miranda , Larry D. Hewitt , Jonathan M. Owen
IPC分类号： G06F1/26
CPC分类号： G06F1/3203 , G06F1/3253 , Y02D10/151 , Y02D50/20
摘要： A computer system includes a first and a second integrated circuit coupled by a communication link. The communication link operates in a power savings mode in which data is not transmitted over the link. Periodically, the communication link enters a training phase in which training patterns are transmitted over the communication link for a predetermined time period. The communication link returns to the power savings mode after the predetermined time period has elapsed. At least one sideband signal, separate from the communication link, and coupled between the first and second integrated circuits, is used to indicate when to enter the training phase from the power savings mode and exit the training phase and return to the power savings mode.
摘要翻译：计算机系统包括通过通信链路耦合的第一和第二集成电路。通信链路以省电模式运行，其中数据不通过链路发送。周期性地，通信链路进入训练阶段，其中通过通信链路在预定时间段内传送训练模式。在预定时间段过去之后，通信链路返回到省电模式。与通信链路分离并且耦合在第一和第二集成电路之间的至少一个边带信号用于指示何时从功率节省模式进入训练阶段并退出训练阶段并返回到省电模式。

2. 发明授权

US07421525B2 System including a host connected to a plurality of memory modules via a serial memory interconnect 有权
标题翻译：系统包括通过串行存储器互连连接到多个存储器模块的主机
公开(公告)号：US07421525B2
公开(公告)日：2008-09-02
申请号：US10842296
申请日：2004-05-10
申请人： R. Stephen Polzin , Frederick D. Weber , Gerald R. Talbot , Larry D. Hewitt , Richard W. Reeves , Shwetal A. Patel , Ross V. La Fetra , Dale E. Gulick , Mark D. Hummel , Paul C. Miranda
发明人： R. Stephen Polzin , Frederick D. Weber , Gerald R. Talbot , Larry D. Hewitt , Richard W. Reeves , Shwetal A. Patel , Ross V. La Fetra , Dale E. Gulick , Mark D. Hummel , Paul C. Miranda
IPC分类号： G06F13/00 , G06F13/28 , G06F12/00 , G11C5/06
CPC分类号： G06F13/4243 , G06F12/0215 , G06F12/0862 , G06F13/1626 , G06F2212/6022
摘要： A system including a host coupled to a serially connected chain of memory modules. In one embodiment, each of the memory modules includes a memory control hub for controlling access to a plurality of memory chips on the memory module. The memory modules are coupled serially in a chain to the host via a plurality of memory links. Each memory link may include an uplink for conveying transactions toward the host and a downlink for conveying transactions originating at the host to a next memory module in the chain. The uplink and the downlink may convey transactions using packets that include control and configuration packets and memory access packets. The memory control hub may convey a transaction received on a first downlink of a first memory link on a second downlink of a second memory link independent of decoding the transaction.
摘要翻译：一种系统，包括耦合到串行连接的存储器模块链的主机。在一个实施例中，每个存储器模块包括用于控制对存储器模块上的多个存储器芯片的访问的存储器控制集线器。存储器模块通过多个存储器链路串联地连接到主机。每个存储器链路可以包括用于向主机传送事务的上行链路和用于将在主机处发起的事务传送到链路中的下一个存储器模块的下行链路。上行链路和下行链路可以使用包括控制和配置分组和存储器访问分组的分组来传送事务。存储器控制集线器可以在第二存储器链路的第二下行链路上传送在第一存储器链路的第一下行链路上接收的事务，而与解码事务无关。

3. 发明申请

US20070230513A1 TRANSMITTER VOLTAGE AND RECEIVER TIME MARGINING 有权
标题翻译：发射器电压和接收器时间限制
公开(公告)号：US20070230513A1
公开(公告)日：2007-10-04
申请号：US11668010
申请日：2007-01-29
申请人： Gerald R. Talbot , Paul C. Miranda , Emerson S. Fang , Rohit Kumar
发明人： Gerald R. Talbot , Paul C. Miranda , Emerson S. Fang , Rohit Kumar
IPC分类号： H04J3/06
CPC分类号： G01R31/30 , G01R31/3004 , G01R31/316 , G01R31/317 , H04L1/20 , H04L7/0337
摘要： A technique for characterizing a communications interface includes determining a voltage margin and a timing margin of the interface based on data sampled by a sampling device of a receiver of the interface. In at least one embodiment of the invention, a method for determining margin associated with a receiver circuit of an integrated circuit includes periodically sampling a signal over a time period by a receiver sampling circuit of the receiver circuit to generate a sampled version of the signal. The method includes incrementally varying a value of the parameter associated with the signal. The varying of the parameter is through a range of values of the parameter over the time period. The method includes determining a margin value of the receiver circuit associated with the parameter based, at least in part, on the sampled version of the signal.
摘要翻译：用于表征通信接口的技术包括基于由接口的接收机的采样设备采样的数据来确定接口的电压余量和定时裕度。在本发明的至少一个实施例中，用于确定与集成电路的接收机电路相关联的裕量的方法包括由接收机电路的接收机采样电路在一段时间周期性地对信号进行采样以产生信号的采样版本。该方法包括递增地改变与信号相关联的参数的值。参数的变化是通过该时间段内参数值的范围。该方法包括至少部分地基于信号的采样版本来确定与参数相关联的接收机电路的边缘值。

4. 发明申请

US20130077701A1 METHOD AND INTEGRATED CIRCUIT FOR ADJUSTING THE WIDTH OF AN INPUT/OUTPUT LINK 审中-公开
标题翻译：用于调整输入/输出链路宽度的方法和集成电路
公开(公告)号：US20130077701A1
公开(公告)日：2013-03-28
申请号：US13243086
申请日：2011-09-23
申请人： Benjamin Tsien , Kevin M. Lepak , Paul C. Miranda , William A. Hughes , Wade L. Williams , Chenping Yang , Adam L. From
发明人： Benjamin Tsien , Kevin M. Lepak , Paul C. Miranda , William A. Hughes , Wade L. Williams , Chenping Yang , Adam L. From
IPC分类号： H04L27/00
CPC分类号： G06F1/3253 , G06F13/4273 , H04L25/14 , H04W28/18 , Y02D10/151
摘要： A method and apparatus are described for adjusting a bit width of an input/output (I/O) link established between a transmitter and a receiver. The I/O link has a plurality of bit lanes. The transmitter may send to the receiver a command identifying at least one selected bit lane of the I/O link that will be powered off or powered on in response to detecting that a bit width adjustment threshold of the I/O link has been reached.
摘要翻译：描述了一种用于调整在发射机和接收机之间建立的输入/输出（I / O）链路的比特宽度的方法和装置。 I / O链路具有多个位通道。响应于检测到已经达到I / O链路的比特宽度调整阈值，发射机可以向接收机发送识别I / O链路的至少一个所选比特通道的命令，该I / O链路将被断电或上电。

5. 发明授权

US08402241B2 Method and apparatus to control access to device enable features 有权
标题翻译：控制对设备启用功能的访问的方法和设备
公开(公告)号：US08402241B2
公开(公告)日：2013-03-19
申请号：US11866211
申请日：2007-10-02
申请人： Paul C. Miranda , Kenneth Alan House , Charles K. Bachand
发明人： Paul C. Miranda , Kenneth Alan House , Charles K. Bachand
IPC分类号： G06F12/00
CPC分类号： G06F12/1466 , G06F2212/2022 , G11C7/1045 , G11C7/24 , G11C8/20 , G11C16/22 , G11C17/18
摘要： An integrated circuit device includes a first plurality of non-volatile memory locations such as fuses that supply programmed values corresponding to initially selected device features such as voltage, frequency, clock speed, and cache parameters. The device is programmed with a lock value in a second plurality of non-volatile memory locations. That lock value may be a randomly generated number that is unique for each device. After initial programming of the device, access to the device is prevented by appropriately programming access control. In order to unlock the device and modify device features, an unlock key value is supplied to the device. If the unlock key value correctly corresponds to the lock value, the device features can be modified. In that way device features can be modified, but security is maintained to prevent unauthorized modification to device features.
摘要翻译：集成电路设备包括第一多个非易失性存储器位置，例如提供对应于最初选择的设备特征（诸如电压，频率，时钟速度和高速缓存参数）的编程值的熔丝。该装置在第二多个非易失性存储器位置中以锁定值编程。该锁值可以是每个设备唯一的随机生成的数字。在设备的初始编程之后，通过适当地编程访问控制来防止对设备的访问。为了解锁设备和修改设备功能，解锁键值被提供给设备。如果解锁键值正确对应于锁定值，则可以修改设备功能。这样可以修改设备功能，但是保持安全性，以防止对设备功能的未经授权的修改。

6. 发明申请

US20080229174A1 ERROR DETECTION IN A COMMUNICATIONS LINK 有权
标题翻译：通信链路中的错误检测
公开(公告)号：US20080229174A1
公开(公告)日：2008-09-18
申请号：US11685263
申请日：2007-03-13
申请人： Paul C. Miranda
发明人： Paul C. Miranda
IPC分类号： H03M13/09
CPC分类号： H03M13/091
摘要： An integrated circuit communications interface operable consistent with multiple data transmission protocols includes error detection circuitry that implements a cyclic redundancy check (i.e., CRC) function. The error detection circuitry generates a checksum based, at least in part, on a selected one of the multiple data transmission protocols. The error detection circuitry includes at least one circuit that generates a digital code according to an operation including terms common to the multiple data transmission protocols. That digital code is combined with a selected digital code to generate the CRC. The selected digital code is generated by an individual circuit corresponding to a respective one of the multiple data transmission protocols. The individual circuit generates the selected digital code according to an operation including at least terms exclusive to the respective one of the multiple data transmission protocols.
摘要翻译：可与多个数据传输协议一致操作的集成电路通信接口包括实现循环冗余校验（即CRC）功能的错误检测电路。所述错误检测电路至少部分地基于所选择的多个数据传输协议之一生成校验和。误差检测电路包括至少一个根据包括多个数据传输协议共同的术语的操作产生数字码的电路。该数字代码与选定的数字代码组合以产生CRC。所选择的数字码由与多个数据传输协议中的相应一个对应的单独电路产生。单独电路根据包括多个数据传输协议中的相应一个专用的至少术语的操作来生成所选择的数字代码。

7. 发明授权

US08000404B2 Method and apparatus to reduce the effect of crosstalk in a communications interface 有权
标题翻译：降低通信接口串扰影响的方法和装置
公开(公告)号：US08000404B2
公开(公告)日：2011-08-16
申请号：US11627586
申请日：2007-01-26
申请人： Gerald R. Talbot , Paul C. Miranda
发明人： Gerald R. Talbot , Paul C. Miranda
IPC分类号： H04B15/00
CPC分类号： H04L25/03866 , H04L25/085 , H04L25/45
摘要： A technique for reducing crosstalk between communications paths includes scrambling data using scrambling functions that reduce or substantially minimize a probability that worst-case data patterns occur on communications paths adjacent to a potential victim communications path. In at least one embodiment of the invention, a method includes scrambling a plurality of data bits based at least in part on respective ones of a plurality of distinct combinations of one or more taps of a linear feedback shift register (LFSR). The plurality of data bits are scrambled for transmission during a first bit-time on corresponding ones of a plurality of adjacent communications paths.
摘要翻译：用于减少通信路径之间的串扰的技术包括使用减少或基本上最小化最差情况数据模式在与潜在受害者通信路径相邻的通信路径上发生的概率的加扰数据的加扰数据。在本发明的至少一个实施例中，一种方法包括至少部分地基于线性反馈移位寄存器（LFSR）的一个或多个抽头的多个不同组合中的相应的数据位来对多个数据位进行加扰。多个数据比特被加扰以便在多个相邻通信路径中的相应的一个的第一比特时间内进行传输。

8. 发明授权

US07617404B2 In-band power management in a communication link 有权
标题翻译：通信链路中的带内功率管理
公开(公告)号：US07617404B2
公开(公告)日：2009-11-10
申请号：US11482211
申请日：2006-07-07
申请人： Paul A. Mackey , Paul C. Miranda , Larry D. Hewitt , Jonathan M. Owen
发明人： Paul A. Mackey , Paul C. Miranda , Larry D. Hewitt , Jonathan M. Owen
IPC分类号： G06F1/26
CPC分类号： G06F1/3203 , G06F1/3237 , G06F1/3287 , Y02D10/128 , Y02D10/171 , Y02D50/20
摘要： A first portion of a communication link is operated in a power savings mode at the same time that a second portion of the communication link is operated in a normal operational mode. For the first portion, a refresh mode is entered from the power savings mode in which one or more training patterns are transmitted over the first portion, while the second portion remains in the normal operational mode. An indication when to activate and deactivate the refresh mode may be sent over the second portion of the communication link. The refresh mode may be periodically entered from the power savings mode based on an interval register specifying the amount of time the communication link should remain in the power savings mode before a refresh occurs. In addition, the amount of time spent in the refresh mode may be programmable.
摘要翻译：在通信链路的第二部分以正常操作模式操作的同时，通信链路的第一部分以省电模式操作。对于第一部分，从功率节省模式输入刷新模式，其中在第一部分上发送一个或多个训练模式，而第二部分保持在正常操作模式。激活和去激活刷新模式的指示可以在通信链路的第二部分上发送。可以基于指定在刷新发生之前通信链路应该保持在省电模式的时间量的间隔寄存器，从省电模式周期性地进入刷新模式。此外，在刷新模式下花费的时间量可以是可编程的。

9. 发明申请

US20090089529A1 METHOD AND APPARATUS TO CONTROL ACCESS TO DEVICE ENABLE FEATURES 有权
标题翻译：控制设备启用特性的方法和设备
公开(公告)号：US20090089529A1
公开(公告)日：2009-04-02
申请号：US11866211
申请日：2007-10-02
申请人： Paul C. Miranda , Kenneth Alan House , Charles K. Bachand
发明人： Paul C. Miranda , Kenneth Alan House , Charles K. Bachand
IPC分类号： G06F12/14
CPC分类号： G06F12/1466 , G06F2212/2022 , G11C7/1045 , G11C7/24 , G11C8/20 , G11C16/22 , G11C17/18
摘要： An integrated circuit device includes a first plurality of non-volatile memory locations such as fuses that supply programmed values corresponding to initially selected device features such as voltage, frequency, clock speed, and cache parameters. The device is programmed with a lock value in a second plurality of non-volatile memory locations. That lock value may be a randomly generated number that is unique for each device. After initial programming of the device, access to the device is prevented by appropriately programming access control. In order to unlock the device and modify device features, an unlock key value is supplied to the device. If the unlock key value correctly corresponds to the lock value, the device features can be modified. In that way device features can be modified, but security is maintained to prevent unauthorized modification to device features.
摘要翻译：集成电路设备包括第一多个非易失性存储器位置，例如提供对应于最初选择的设备特征（诸如电压，频率，时钟速度和高速缓存参数）的编程值的熔丝。该装置在第二多个非易失性存储器位置中以锁定值编程。该锁值可以是每个设备唯一的随机生成的数字。在设备的初始编程之后，通过适当地编程访问控制来防止对设备的访问。为了解锁设备和修改设备功能，解锁键值被提供给设备。如果解锁键值正确对应于锁定值，则可以修改设备功能。这样可以修改设备功能，但是保持安全性，以防止对设备功能的未经授权的修改。

10. 发明申请

US20070230553A1 IN-BAND METHOD TO CONFIGURE EQUALIZATION LEVELS 有权
标题翻译：配置均衡水平的内嵌方法
公开(公告)号：US20070230553A1
公开(公告)日：2007-10-04
申请号：US11614529
申请日：2006-12-21
申请人： Gerald R. Talbot , Larry D. Hewitt , Paul C. Miranda
发明人： Gerald R. Talbot , Larry D. Hewitt , Paul C. Miranda
IPC分类号： H03H7/30
CPC分类号： H04L25/03878 , H04L7/0008 , H04L7/0091 , H04L2025/03592
摘要： An in-band configuration technique configures a data communications link for high-speed data communications between at least a first and second integrated circuit using in-band communications between the first and second integrated circuits. The technique configures at least one equalizer of the data communications link with predetermined equalizer settings selected from a plurality of predetermined equalizer settings based on a selected rate of data communications for the link.
摘要翻译：带内配置技术使用第一和第二集成电路之间的带内通信来配置用于在至少第一和第二集成电路之间的高速数据通信的数据通信链路。该技术基于针对该链路的所选择的数据通信速率，从至少一个预定均衡器设置中选择的预定均衡器设置配置数据通信链路的至少一个均衡器。

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