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1. 发明授权

US06466479B2 Non-volatile memory matrix architecture with vertical insulation strips between adjacent memory blocks 有权
标题翻译：非易失性存储器矩阵结构，在相邻存储块之间具有垂直绝缘条
公开(公告)号：US06466479B2
公开(公告)日：2002-10-15
申请号：US09898744
申请日：2001-07-03
申请人： Paolo Rolandi
发明人： Paolo Rolandi
IPC分类号： G11C1604
CPC分类号： G11C16/08 , G11C16/0491 , H01L27/115
摘要： A non-volatile memory matrix architecture, having a virtual ground monolithically integrated on a semiconductor substrate, includes a plurality of memory cells organized into matrix blocks. The matrix blocks are placed on rows and columns and are associated with respective row and column decoding circuits. The memory blocks are separated from each other by at least one insulation stripe which is parallel to the columns. The non-volatile memory matrix architecture further includes a pass-transistor decoding circuit with a number of levels corresponding to the number of rows to select.
摘要翻译：具有单片集成在半导体衬底上的虚拟接地的非易失性存储矩阵体系包括被组织成矩阵块的多个存储单元。矩阵块被放置在行和列上并且与相应的行和列解码电路相关联。存储块通过平行于列的至少一个绝缘条彼此分离。非易失性存储器矩阵架构还包括具有对应于要选择的行数的多个级别的传输晶体管解码电路。

2. 发明授权

US6097628A Multi-level memory circuit with regulated writing voltage 有权
标题翻译：具有稳压写电压的多电平存储电路
公开(公告)号：US6097628A
公开(公告)日：2000-08-01
申请号：US202656
申请日：1999-06-07
申请人： Paolo Rolandi
发明人： Paolo Rolandi
IPC分类号： G11C16/02 , G11C11/56 , G11C11/34
CPC分类号： G11C11/5621 , G11C11/5628 , G11C16/30 , G11C5/145
摘要： A multi-level memory circuit for binary information includes a plurality of memory cells each adapted to store more than one item of binary information, and each memory cell includes at least one floating gate MOS transistor. The information stored therein corresponds to the level of the cell threshold voltage. A write signal generating circuit is adapted to an input supply voltage and provides a write voltage to the memory cells. The write signal generating circuit generates internally at least one write voltage having a selectable or selected value from a number of discrete regulated values corresponding to the number of the discrete levels provided.
摘要翻译： PCT No.PCT / IT96 / 00199 Sec。 371日期1999年6月7日 102（e）1999年6月7日PCT PCT 1996年10月30日PCT公布。第WO97 / 49088号公报日期1997年12月24日用于二进制信息的多级存储器电路包括多个存储单元，每个存储单元适于存储多于一个二进制信息项，并且每个存储单元包括至少一个浮置栅极MOS晶体管。存储在其中的信息对应于单元阈值电压的电平。写入信号发生电路适于输入电源电压并向存储器单元提供写入电压。写入信号发生电路在内部产生至少一个写入电压，该写入电压具有与所提供的离散电平的数量相对应的多个离散调节值的可选择或选择的值。

3. 发明授权

US07529881B2 Method for accessing in reading, writing and programming to a nand non-volatile memory electronic device monolithically integrated on semiconductor 有权
标题翻译：用于在单片集成在半导体上的nand非易失性存储器电子器件中进行读取，写入和编程的访问方法
公开(公告)号：US07529881B2
公开(公告)日：2009-05-05
申请号：US11561799
申请日：2006-11-20
申请人： Luigi Pascucci , Paolo Rolandi
发明人： Luigi Pascucci , Paolo Rolandi
IPC分类号： G06F13/00
CPC分类号： G11C5/066 , G11C7/1018 , G11C7/1045 , G11C16/0483 , G11C16/08 , G11C2207/105
摘要： A method for accessing, in reading, programming, and erasing a semiconductor-integrated non-volatile memory device of the Flash EEPROM type with a NAND architecture having at least one memory matrix organized in rows or word lines and columns or bit lines, and wherein, for the memory, a plurality of additional address pins are provided. The method provides both an access protocol of the asynchronous type and a protocol of the extended type allowing to address, directly and in parallel, a memory extended portion by loading an address register associated with the additional pins in two successive clock pulses. A third multi-sequential access mode and a parallel additional bus referring to the additional address pins are also provided to allow a double addressing mode, sequential and in parallel.
摘要翻译：一种用于以具有至少一个以行或字线和列或位线组织的存储矩阵的NAND架构来访问，读取，编程和擦除闪存EEPROM类型的半导体集成非易失性存储器件的方法，其中为了存储器，提供了多个附加的地址引脚。该方法提供异步类型的访问协议和扩展类型的协议，允许通过在两个连续的时钟脉冲中加载与附加引脚相关联的地址寄存器来直接和并行地寻址存储器扩展部分。还提供了第三个多序列访问模式和引用附加地址引脚的并行附加总线，以允许双寻址模式，顺序和并行。

4. 发明授权

US07525851B2 Row decoder circuit and related system and method 有权
标题翻译：行解码电路及相关系统及方法
公开(公告)号：US07525851B2
公开(公告)日：2009-04-28
申请号：US11434564
申请日：2006-05-15
申请人： Luigi Pascucci , Paolo Rolandi
发明人： Luigi Pascucci , Paolo Rolandi
IPC分类号： G11C5/14
CPC分类号： G11C8/10 , G11C16/08
摘要： A row decoder circuit is described of the type comprising at least one input stage connected to a first supply voltage reference and to an output stage connected to a second supply voltage reference, the output stage having at least one output terminal connected to a word line of a memory matrix. The row decoder circuit further comprises a biasing device, connected to a third supply voltage reference and comprising at least one generator of a negative voltage connected to a divider, in turn connected to a first biasing terminal of the biasing device. In particular, the first biasing terminal is connected to at least one input stage in correspondence with bulk terminals of MOS transistors comprised in the input stage and it is suitable for supplying it with a first negative voltage.
摘要翻译：描述了包括连接到第一电源电压基准的至少一个输入级和连接到第二电源电压基准的输出级的类型的行解码器电路，所述输出级具有至少一个输出端子连接到字线一个记忆矩阵行解码器电路还包括偏置装置，其连接到第三电源参考电压并且包括连接到分压器的负电压的至少一个发生器，该发电机又连接到偏置装置的第一偏置端子。特别地，第一偏置端子与至少一个输入级连接，对应于包含在输入级中的MOS晶体管的体积端子，并且适合于向第一偏置端子提供第一负电压。

5. 发明申请

US20090027965A1 ROW SELECTOR CIRCUIT FOR ELECTRICALLY PROGRAMMABLE AND ERASABLE NON VOLATILE MEMORIES 有权
标题翻译：电可编程和可擦除非易失性存储器的选择电路
公开(公告)号：US20090027965A1
公开(公告)日：2009-01-29
申请号：US12244717
申请日：2008-10-02
申请人： Paolo Rolandi
发明人： Paolo Rolandi
IPC分类号： G11C16/04 , G11C16/06 , G11C8/08
CPC分类号： G11C8/10 , G11C16/16
摘要： The invention relates to a row decoder circuit for non volatile memory devices of the electrically programmable and erasable type, for example of the Flash EEPROM type having a NOR architecture. The proposed row decoder circuit allows to carry out the erasing step very quickly, for example with a granularity emulating at least 16 kB and even overcoming by at least 2 kB Flash memories of the NAND type. The memory can thus maintain high performances in terms of random access speed but shows a high erasing speed typical of memory architectures of the NAND type.
摘要翻译：本发明涉及一种用于电可编程和可擦除类型的非易失性存储器件的行解码器电路，例如具有NOR架构的闪速EEPROM类型。所提出的行解码器电路允许非常快速地执行擦除步骤，例如，以至少16kB的粒度并且甚至由NAND类型的至少2kB的闪存来克服的粒度。因此，存储器可以在随机访问速度方面保持高性能，但是显示出NAND类型的存储器架构的典型的高擦除速度。

6. 发明授权

US07417900B2 Method and system for refreshing a memory device during reading thereof 有权
标题翻译：读取时刷新存储器件的方法和系统
公开(公告)号：US07417900B2
公开(公告)日：2008-08-26
申请号：US11695552
申请日：2007-04-02
申请人： Paolo Rolandi , Luigi Pascucci
发明人： Paolo Rolandi , Luigi Pascucci
IPC分类号： G11C16/06
CPC分类号： G11C16/3431 , G11C11/5628 , G11C16/3418
摘要： A refresh circuit for refreshing a memory device is proposed. The refresh circuit includes: reading means for reading a set of memory cells, the reading means including means for applying a biasing voltage having a substantially monotone time pattern to the memory cells and to a set of reference cells each one having a reference threshold voltage, means for detecting the reaching of a comparison current by a cell current of each memory cell and by a reference current of each reference cell, and means for determining a condition of each memory cell according to a temporal relation of the reaching of the comparison current by the corresponding cell current and the reference currents, and writing means for applying a writing voltage to at least one selected of the memory cells; the refresh circuit further includes control means for enabling the writing means during at least part of the application of the biasing voltage after the determination of the condition of each selected memory cell.
摘要翻译：提出了刷新存储器件的刷新电路。刷新电路包括：用于读取一组存储单元的读取装置，所述读取装置包括用于向存储单元施加具有基本上单调的时间模式的偏置电压的装置和具有参考阈值电压的一组参考单元，用于通过每个存储单元的单元电流和每个参考单元的参考电流来检测比较电流达到的装置，以及用于根据达到比较电流的时间关系确定每个存储单元的状态的装置对应的单元电流和参考电流;以及写入装置，用于向至少一个选择的存储单元施加写入电压; 刷新电路还包括控制装置，用于在确定每个所选择的存储单元的状态之后，在施加偏置电压的至少一部分期间使写入装置能够使能。

7. 发明申请

US20070153578A1 METHOD FOR ACCESSING IN READING, WRITING AND PROGRAMMING TO A NAND NON-VOLATILE MEMORY ELECTRONIC DEVICE MONOLITHICALLY INTEGRATED ON SEMICONCTOR 有权
标题翻译：读取，写入和编程到NAND单片存储器电子器件的方法，该器件可以单一地集成在SEMICONCTOR
公开(公告)号：US20070153578A1
公开(公告)日：2007-07-05
申请号：US11561799
申请日：2006-11-20
申请人： Luigi Pascucci , Paolo Rolandi
发明人： Luigi Pascucci , Paolo Rolandi
IPC分类号： G11C16/04
CPC分类号： G11C5/066 , G11C7/1018 , G11C7/1045 , G11C16/0483 , G11C16/08 , G11C2207/105
摘要： A method for accessing, in reading, programming, and erasing a semiconductor-integrated non-volatile memory device of the Flash EEPROM type with a NAND architecture having at least one memory matrix organized in rows or word lines and columns or bit lines, and wherein, for the memory, a plurality of additional address pins are provided. The method provides both an access protocol of the asynchronous type and a protocol of the extended type allowing to address, directly and in parallel, a memory extended portion by loading an address register associated with the additional pins in two successive clock pulses. A third multi-sequential access mode and a parallel additional bus referring to the additional address pins are also provided to allow a double addressing mode, sequential and in parallel.
摘要翻译：一种用于以具有至少一个以行或字线和列或位线组织的存储矩阵的NAND架构来访问，读取，编程和擦除闪存EEPROM类型的半导体集成非易失性存储器件的方法，其中为了存储器，提供了多个附加的地址引脚。该方法提供异步类型的访问协议和扩展类型的协议，允许通过在两个连续的时钟脉冲中加载与附加引脚相关联的地址寄存器来直接和并行地寻址存储器扩展部分。还提供了第三个多次访问模式和引用附加地址引脚的并行附加总线，以允许双寻址模式，顺序和并行。

8. 发明申请

US20060274577A1 NON-VOLATILE MEMORY ELECTRONIC DEVICE WITH NAND STRUCTURE BEING MONOLITHICALLY INTEGRATED ON SEMICONDUCTOR 有权
标题翻译：具有NAND结构的非易失性存储器件电子器件单一集成在半导体
公开(公告)号：US20060274577A1
公开(公告)日：2006-12-07
申请号：US11279381
申请日：2006-04-11
申请人： Luigi Pascucci , Paolo Rolandi
发明人： Luigi Pascucci , Paolo Rolandi
IPC分类号： G11C16/04
CPC分类号： G11C16/08 , G11C16/0408 , G11C16/0483 , G11C16/12 , G11C16/24 , Y10T29/49002
摘要： A non-volatile memory electronic device is integrated on a semiconductor and is of the Flash EEPROM type with an architecture of the NAND type including at least one memory matrix organized in rows or word lines and columns or bit lines of memory cells and with at least one associated row decoding circuit portion. Advantageously, the matrix includes at least one logic sector with pairs of rows or word lines being short-circuited with each other and referring to a respective biasing terminal, one for each pair, and in that the row decoding circuit portion includes a single select block which controls a single multiplexer for the logic sector for the regulation of the signals applied to the biasing terminals.
摘要翻译：非易失性存储器电子器件被集成在半导体上并且是具有NAND类型的架构的闪存EEPROM类型，其包括以行或字线和存储器单元的列或位线组织的至少一个存储器矩阵，并且至少具有一个相关联的行解码电路部分。有利地，矩阵包括至少一个逻辑扇区，其中成对的行或字线彼此短路并且参考相应的偏置端子，每对一个，并且行解码电路部分包括单个选择块其控制用于逻辑扇区的单个多路复用器用于调节施加到偏置端子的信号。

9. 发明申请

US20060227610A1 INTEGRATED ELECTRONIC NON VOLATILE MEMORY DEVICE HAVING NAND STRUCTURE 有权
标题翻译：具有NAND结构的集成电子非易失性存储器件
公开(公告)号：US20060227610A1
公开(公告)日：2006-10-12
申请号：US11279384
申请日：2006-04-11
申请人： Luigi Pascucci , Paolo Rolandi
发明人： Luigi Pascucci , Paolo Rolandi
IPC分类号： G11C16/04
CPC分类号： G11C16/08 , G11C16/0408 , G11C16/0483 , G11C16/12 , G11C16/24 , Y10T29/49002
摘要： A non-volatile memory electronic device is integrated on a semiconductor and is of the Flash EEPROM type with an architecture of the NAND type including at least one memory matrix divided into sectors being singularly erasable and organized in rows or word lines and columns or bit lines of memory cells. Advantageously, the matrix may include logic sectors wherein pairs of rows or word lines are electrically short-circuited and refer to a single biasing terminal, source terminals of the associated cells of each pair of rows associated with a same source select line referring to a corresponding biasing terminal, and at least one pair of independent drain select lines, each of the rows and of the lines being provided with metallization shunts to by-pass groups of bit lines and/or to speed up the propagation times of the biasing in the corresponding logic sector.
摘要翻译：非易失性存储器电子器件集成在半导体上，并且是具有NAND型结构的闪存EEPROM类型，包括被划分成扇区的至少一个存储器矩阵，其被单独地擦除并且被组织成行或字线和列或位线的记忆细胞。有利地，矩阵可以包括其中行或字线对被电短路并且指代单个偏置端子的逻辑扇区，每对行的相关联的单元的源极端子与相应的源选择线相关联，其指向相应的偏置端子以及至少一对独立的漏极选择线，行和行中的每一行被设置有金属化分流器以逐行排列组和/或加速相应的偏置的传播时间逻辑部门。

10. 发明授权

US07075844B2 Parallel sense amplifier with mirroring of the current to be measured into each reference branch 失效
标题翻译：并行感测放大器将要测量的电流与每个参考分支进行镜像
公开(公告)号：US07075844B2
公开(公告)日：2006-07-11
申请号：US10762195
申请日：2004-01-20
申请人： Mauro Pagliato , Massimo Montanaro , Paolo Rolandi
发明人： Mauro Pagliato , Massimo Montanaro , Paolo Rolandi
IPC分类号： G11C7/02
CPC分类号： G11C16/28
摘要： A parallel sense amplifier includes a measuring branch for receiving an input current to be measured, a plurality of reference branches each one for receiving a reference current, and a plurality of comparators each one for comparing a voltage at a measuring node along the measuring branch with a voltage at a reference node along a corresponding reference branch; the amplifier further includes a multiple current mirror for mirroring the input current into each reference branch.
摘要翻译：并行读出放大器包括用于接收待测量的输入电流的测量分支，每个用于接收参考电流的多个参考分支;以及多个比较器，每个比较器用于将沿着测量分支的测量节点处的电压与沿着相应参考分支的参考节点处的电压; 放大器还包括用于将输入电流镜像到每个参考分支中的多电流镜。

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