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1. 发明授权

US08645594B2 Driver-assisted base address register mapping 有权
标题翻译：驱动程序辅助基地址寄存器映射
公开(公告)号：US08645594B2
公开(公告)日：2014-02-04
申请号：US13538221
申请日：2012-06-29
申请人： Annie Foong , Pak-Lung Seto
发明人： Annie Foong , Pak-Lung Seto
IPC分类号： G06F13/38
CPC分类号： G06F12/063
摘要： Techniques herein include systems and methods for driver-assisted BAR mapping that virtualize PCI functions, but without virtualizing the storage media itself. Such techniques make use of unused BARs (Base Address Registers) of a master (Operating system-facing) device to gain access to other PCIe logical instances, while still exposing only a single PCIe function (connection or channel) to system software. This technique provides a new concept of logical PCIe device instances through BAR mapping by making use of unused BARs to extend access to any number of PCIe instances or memory-mapped I/O devices behind a master device such that only a single PCIe function is exposed to system software. Embodiments can thus extend access to one or more additional storage devices through one level of BAR indirection. As a result, such techniques and embodiments enable the multiplication of storage capacity and performance through the aggregation of multiple, similar hardware components.
摘要翻译：本文的技术包括用于驱动器辅助BAR映射的系统和方法，其虚拟化PCI功能，但不虚拟存储介质本身。这种技术利用主（面向操作系统）设备的未使用的BAR（基地址寄存器）来访问其他PCIe逻辑实例，同时仍然仅向系统软件公开单个PCIe功能（连接或通道）。该技术通过使用未使用的BAR来扩展对主设备后面的任何数量的PCIe实例或存储器映射的I / O设备的访问，从而通过BAR映射提供了逻辑PCIe设备实例的新概念，使得只有一个PCIe功能被暴露到系统软件。因此，实施例可以通过一个BAR间接级别来扩展对一个或多个附加存储设备的访问。结果，这些技术和实施例能够通过聚合多个类似的硬件组件来增加存储容量和性能。

2. 发明授权

US08032675B2 Dynamic memory buffer allocation method and system 有权
标题翻译：动态内存缓冲区分配方法和系统
公开(公告)号：US08032675B2
公开(公告)日：2011-10-04
申请号：US11320392
申请日：2005-12-28
申请人： Naichih Chang , Pak-Lung Seto , Victor Lau
发明人： Naichih Chang , Pak-Lung Seto , Victor Lau
IPC分类号： G06F3/00 , G06F5/00
CPC分类号： G06F12/023
摘要： A method, computer program product, system (including a circuit card), and integrated circuit for initializing a buffer pool, such that the buffer pool includes a plurality of data buffers available for use during a plurality of I/O transfers. In response to the initiation of a first I/O transfer concerning a first data portion being transferred from a first data source to a first data target, the first data portion is written to a first portion of the plurality of data buffers. The first data portion is transferred to the first data target, and the first portion of the plurality of data buffers is released back to the buffer pool for use during one or more subsequent I/O transfers.
摘要翻译：一种方法，计算机程序产品，系统（包括电路卡）和用于初始化缓冲池的集成电路，使得缓冲器池包括可在多个I / O传输期间使用的多个数据缓冲器。响应于关于从第一数据源传送到第一数据目标的第一数据部分的第一I / O传送的开始，第一数据部分被写入多个数据缓冲器的第一部分。第一数据部分被传送到第一数据目标，并且多个数据缓冲器的第一部分被释放回缓冲池，以在一个或多个后续的I / O传输期间使用。

3. 发明授权

US07984208B2 Method using port task scheduler 有权
标题翻译：使用端口任务调度器的方法
公开(公告)号：US07984208B2
公开(公告)日：2011-07-19
申请号：US12268026
申请日：2008-11-10
申请人： Tracey Gustafson , Pak-lung Seto , Gary Y. Tsao , Nai-Chih Chang , Victor Lau
发明人： Tracey Gustafson , Pak-lung Seto , Gary Y. Tsao , Nai-Chih Chang , Victor Lau
IPC分类号： G06F15/173 , G06F3/00 , G06F13/14 , G06F13/36 , G06F9/46
CPC分类号： G06F13/126 , G06F13/385
摘要： According to one embodiment, an apparatus is disclosed. The apparatus includes a port having a plurality of lanes, a plurality of protocol engines. Each protocol engine is associated with one of the plurality of lanes, and processes tasks to be forwarded to a plurality of remote nodes. The apparatus also includes a first port task scheduler (PTS) to manage the tasks to be forwarded to the one or more of the plurality of protocol engines. The first PTS includes a register to indicate which of the plurality of protocol engines the first PTS is to support.
摘要翻译：根据一个实施例，公开了一种装置。该装置包括具有多个通道的端口，多个协议引擎。每个协议引擎与多个通道之一相关联，并且处理要转发到多个远程节点的任务。该装置还包括用于管理要转发到多个协议引擎中的一个或多个协议引擎的任务的第一端口任务调度器（PTS）。第一PTS包括一个寄存器，用于指示第一PTS要支持的多个协议引擎中的哪一个。

4. 发明授权

US07805543B2 Hardware oriented host-side native command queuing tag management 有权
标题翻译：面向硬件的主机端本机命令排队标签管理
公开(公告)号：US07805543B2
公开(公告)日：2010-09-28
申请号：US11172715
申请日：2005-06-30
申请人： Naichih Chang , Victor Lau , Pak-lung Seto
发明人： Naichih Chang , Victor Lau , Pak-lung Seto
IPC分类号： G06F3/00 , G06F13/00 , G06F5/00 , G06F13/12 , G06F13/38
CPC分类号： G06F3/0659 , G06F3/0613 , G06F3/0658 , G06F3/0674 , G06F3/0679
摘要： Methods and apparatus for host-side Serial ATA Native Command Queuing (NCQ) tag management are disclosed. In one aspect, an exemplary apparatus may include a memory and an NCQ tag selection circuit in communication with the memory. The memory may store information for each of a plurality of different NCQ tag values. The information for each NCQ tag value may indicate whether or not a command having the NCQ tag value has been issued. The NCQ tag selection circuit may examine the information in the memory, and may select an NCQ tag value having information that indicates that a command having the NCQ tag value has not been issued. Systems and architectures including such apparatus are also disclosed.
摘要翻译：公开了主机侧串行ATA本地命令队列（NCQ）标签管理的方法和装置。在一个方面，示例性装置可以包括与存储器通信的存储器和NCQ标签选择电路。存储器可以存储用于多个不同NCQ标签值中的每一个的信息。每个NCQ标签值的信息可以指示是否已经发出具有NCQ标签值的命令。 NCQ标签选择电路可以检查存储器中的信息，并且可以选择具有指示没有发出具有NCQ标签值的命令的信息的NCQ标签值。还公开了包括这种装置的系统和架构。

5. 发明授权

US07774575B2 Integrated circuit capable of mapping logical block address data across multiple domains 有权
标题翻译：集成电路能够跨多个域映射逻辑块地址数据
公开(公告)号：US07774575B2
公开(公告)日：2010-08-10
申请号：US10945755
申请日：2004-09-21
申请人： Pak-Lung Seto , Martin M. Massucci
发明人： Pak-Lung Seto , Martin M. Massucci
IPC分类号： G06F12/00
CPC分类号： G06F3/0665 , G06F3/0605 , G06F3/0638 , G06F3/0683
摘要： A method according to one embodiment may include discovering at least one data block comprising logical block address information. The method may also include mapping logical block address information from a first domain into a second domain. Of course, many alternatives, variations, and modifications are possible without departing from this embodiment.
摘要翻译：根据一个实施例的方法可以包括发现包括逻辑块地址信息的至少一个数据块。该方法还可以包括将来自第一域的逻辑块地址信息映射到第二域。当然，在不偏离本实施例的情况下，可以进行许多替代，变化和修改。

6. 发明授权

US07620751B2 Command scheduling and affiliation management for serial attached storage devices 有权
标题翻译：串行连接存储设备的命令调度和归属管理
公开(公告)号：US07620751B2
公开(公告)日：2009-11-17
申请号：US11237449
申请日：2005-09-27
申请人： Nai-Chih Chang , Victor Lau , Pak-lung Seto
发明人： Nai-Chih Chang , Victor Lau , Pak-lung Seto
IPC分类号： G06F3/00 , G06F13/12 , G06F13/38 , G06F5/00
CPC分类号： G06F3/0659 , G06F3/0611 , G06F3/0676
摘要： According to one embodiment, a host device is disclosed. The host device includes a logic component to provide an indication of a number of commands issued to a target device, and a task scheduler to schedule commands based on the number of issued commands provided by the logic component.
摘要翻译：根据一个实施例，公开了一种主机设备。主机设备包括逻辑组件，用于提供发出到目标设备的命令的数量的指示，以及任务调度器，用于基于由逻辑组件提供的发出的命令的数量来调度命令。

7. 发明授权

US07502865B2 Addresses assignment for adaptor interfaces 有权
标题翻译：解决适配器接口的分配
公开(公告)号：US07502865B2
公开(公告)日：2009-03-10
申请号：US10742302
申请日：2003-12-18
申请人： Pak-Lung Seto
发明人： Pak-Lung Seto
IPC分类号： G06F15/173
CPC分类号： H04L29/06 , H04L29/12009 , H04L29/12254 , H04L61/00 , H04L61/2038 , H04L69/32
摘要： Provided are a method, system, and article of manufacture for assigning addresses for adaptor interfaces. An initial configuration assigning multiple local interfaces to one initial local address is maintained. For each local interface, a remote address of a remote interface on at least one remote device to which the local interface connects is received. The initial local address is used to identify the local interfaces assigned to the initial local address in response to receiving a same remote address for each remote interface connected to the local interfaces assigned the initial local address.
摘要翻译：提供了用于为适配器接口分配地址的方法，系统和制品。保持将多个本地接口分配给一个初始本地地址的初始配置。对于每个本地接口，接收到本地接口连接的至少一个远程设备上的远程接口的远程地址。响应于为连接到分配了初始本地地址的本地接口的每个远程接口接收到相同的远程地址，初始本地地址用于标识分配给初始本地地址的本地接口。

8. 发明授权

US07412540B2 Data encoding and decoding in a data storage system 有权
标题翻译：数据存储系统中的数据编码和解码
公开(公告)号：US07412540B2
公开(公告)日：2008-08-12
申请号：US10815269
申请日：2004-03-31
申请人： Pak-Lung Seto , Deif N. Atallah
发明人： Pak-Lung Seto , Deif N. Atallah
IPC分类号： G06F15/16
CPC分类号： H04L67/1097
摘要： A method according to one embodiment may include transmitting a frame from a transmitting device to a receiving device via a communication network of a data storage system, enabling an encoding operation of the transmitting device to encode decoded data into encoded data and transmitting the encoded data in the frame via the communication network if the receiving device has a decoding operation capable of decoding the encoded data into the decoded data, and disabling the encoding operation and transmitting the decoded data in the frame via the communication network to the receiving device if the receiving device does not have the decoding operation capable of decoding the encoded data into the decoded data. Of course, many alternatives, variations, and modifications are possible without departing from this embodiment.
摘要翻译：根据一个实施例的方法可以包括经由数据存储系统的通信网络将帧从发送设备发送到接收设备，使得发送设备的编码操作能够将解码的数据编码为编码数据并将编码数据发送到如果接收设备具有能够将编码数据解码为解码数据的解码操作，则经由通信网络的帧，并且如果接收设备，则禁止编码操作并且经由通信网络将经解码的数据经由通信网络发送到接收设备不具有能够将编码数据解码成解码数据的解码操作。当然，在不偏离本实施例的情况下，可以进行许多替代，变化和修改。

9. 发明授权

US07376147B2 Adaptor supporting different protocols 有权
标题翻译：适配器支持不同的协议
公开(公告)号：US07376147B2
公开(公告)日：2008-05-20
申请号：US10742029
申请日：2003-12-18
申请人： Pak-Lung Seto , Deif N. Atallah
发明人： Pak-Lung Seto , Deif N. Atallah
IPC分类号： H04J3/16 , H04J3/22
CPC分类号： H04L29/06 , H04L67/1097 , H04L69/18 , H04L69/32
摘要： Provided are a method, adaptor, system, and program for receiving a transmission at one of multiple connections. Information is maintained on storage interconnect architectures and transmission characteristics, wherein the storage interconnect architectures have different transmission characteristics. At least one transmission characteristic of the received transmission is determined and a determination is made from the information of the storage interconnect architecture associated with the determined transmission characteristic. The information on the determined storage interconnect architecture is used to process the transmission and determine a transport layer for the received transmission, wherein there is one transport layer for each supported transport protocol. The transmission is forwarded to the determined transport layer.
摘要翻译：提供了一种用于在多个连接之一接收传输的方法，适配器，系统和程序。在存储互连架构和传输特性上维持信息，其中存储互连架构具有不同的传输特性。确定接收到的传输的至少一个传输特性，并根据与确定的传输特性相关联的存储互连架构的信息进行确定。关于确定的存储互连体系结构的信息用于处理传输并确定用于所接收的传输的传输层，其中每个支持的传输协议具有一个传输层。传输被转发到确定的传输层。

10. 发明授权

US07366817B2 Frame order processing apparatus, systems, and methods 有权
标题翻译：帧顺序处理装置，系统和方法
公开(公告)号：US07366817B2
公开(公告)日：2008-04-29
申请号：US11171959
申请日：2005-06-29
申请人： Nai-chih Chang , Pak-lung Seto , Victor Lau
发明人： Nai-chih Chang , Pak-lung Seto , Victor Lau
IPC分类号： G06F13/36
CPC分类号： H04L49/9094 , G06F3/0601 , G06F5/065 , G06F13/385 , G06F2003/0692 , H04L49/90 , H04L49/9047
摘要： Apparatus and systems, as well as methods and articles, may bridge between a link layer and a transport layer in a multi-lane serial-attached small computer system interface (SCSI)-serial SCSI protocol (SAS-SSP) device. A lane number first-in first-out buffer (FIFO) array may operate to order frame processing such that frames associated with an input-output (IO) stream subset of a plurality of SAS-SSP frames received at a plurality of lane receive buffers are processed in an IO stream subset order.
摘要翻译：设备和系统以及方法和物品可以在多通道串行连接小型计算机系统接口（SCSI） - 串行SCSI协议（SAS-SSP）设备中的链路层和传输层之间桥接。车道号先入先出缓冲器（FIFO）阵列可以操作以对帧处理进行排序，使得与在多个通道接收缓冲器处接收的多个SAS-SSP帧的输入 - 输出（IO）流子集相关联的帧以IO流子集顺序进行处理。

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