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    • 2. 发明申请
    • ELECTRONIC DEVICE HAVING LOW BACKGROUND LUMINESCENCE, A BLACK LAYER, OR ANY COMBINATION THEREOF
    • 具有低背景亮度,黑色层或其任何组合的电子设备
    • WO2007075560A2
    • 2007-07-05
    • PCT/US2006048230
    • 2006-12-18
    • DU PONTPRAKASH SHIVA
    • PRAKASH SHIVA
    • H01L23/48H01J1/62
    • H01L51/442H01L51/5215H01L51/5281H01L51/5284H01L2924/0002Y02E10/549H01L2924/00
    • An electronic device or a process of forming an electronic device can include a first electrode configured to achieve low L background or include a black layer. An electronic device can include a substrate including a user surface. The electronic device can also include a first electrode that includes a first layer, a second layer, and a third layer. The second layer can lie between the first and third layers, and the first electrode can be configured to achieve low L background . The electronic device can further include a second electrode lying farther from the user surface as compared to the first electrode. In another embodiment, a first electrode can include a first layer and a second layer. The second layer can set the work function of the electrode, and the second layer can be a black layer. Processes can be used to form the electronic devices.
    • 电子设备或形成电子设备的过程可以包括被配置为实现低L背景或包括黑色层的第一电极。 电子设备可以包括包括用户表面的基板。 电子设备还可以包括包括第一层,第二层和第三层的第一电极。 第二层可以位于第一层和第三层之间,并且第一电极可以被配置为实现低L背景。 与第一电极相比,电子器件还可包括位于离用户表面更远的第二电极。 在另一个实施例中,第一电极可以包括第一层和第二层。 第二层可以设置电极的功能,第二层可以是黑色层。 可以使用过程来形成电子设备。
    • 9. 发明申请
    • ELECTRONIC DEVICES COMPRISING CONDUCTIVE MEMBERS THAT CONNECT ELECTRODES TO OTHER CONDUCTIVE MEMBERS WITHIN A SUBSTRATE AND PROCESSES FOR FORMING THE ELECTRONIC DEVICES
    • 包含将电极连接到基板中的其他导电构件的导电构件的电子装置和用于形成电子装置的工艺
    • WO2006072024A2
    • 2006-07-06
    • PCT/US2005/047519
    • 2005-12-29
    • E. I. DU PONT DE NEMOURS AND COMPANYYU, GangPRAKASH, Shiva
    • YU, GangPRAKASH, Shiva
    • H01L29/08
    • H01L27/3276H01L2227/323
    • An electronic device includes a substrate including a pixel driving circuit, a first conductive member, and a second conductive member. The first and second conductive members are spaced apart, the first conductive member is connected to the pixel driving circuit, and the second conductive member can be part of a power transmission line. The electronic device also includes an electronic component that includes a first electrode that contacts the first conductive member, a second electrode that is connected to but does not contact the second conductive member, and an organic layer lying between the first and second electrodes. The electronic device also includes a third conductive member that is connected to the second electrode and the second conductive member, and contacts the second conductive member. In one embodiment, a process for forming the electronic device uses the second electrode as a hardmask when removing portions of the first organic layer.
    • 电子装置包括:基板,包括像素驱动电路,第一导电部件和第二导电部件。 第一和第二导电构件间隔开,第一导电构件连接到像素驱动电路,并且第二导电构件可以是电力传输线的一部分。 电子设备还包括电子部件,其包括接触第一导电部件的第一电极,与第二导电部件连接但不与第二导电部件接触的第二电极以及位于第一和第二电极之间的有机层。 电子设备还包括连接到第二电极和第二导电构件并与第二导电构件接触的第三导电构件。 在一个实施例中,当去除第一有机层的部分时,用于形成电子器件的工艺使用第二电极作为硬掩模。
    • 10. 发明申请
    • ARRAY TRANSFORMATION IN A BEHAVIORAL SYNTHESIS TOOL
    • 行为综​​合工具中的阵列转换
    • WO2003077184A1
    • 2003-09-18
    • PCT/US2003/007241
    • 2003-03-07
    • MENTOR GRAPHICS CORPORATIONPRAKASH, ShivaBOWYER, Bryan, DarrellGUTBERLET, Peter, Pius
    • PRAKASH, ShivaBOWYER, Bryan, DarrellGUTBERLET, Peter, Pius
    • G06G7/62
    • G06F17/5045Y10S707/99931
    • A behavioral synthesis tool (14) for generating an integrated circuit design. The tool allows a designer to interactively (18) allocate variables or arrays to memory resources without having to modify a source code description (12) of the integrated circuit (12). The tool reads the source code description (12) and generates a synthesis intermediate format (16) stored in memory. The tool searches the in-memory synthesis format to find arrays for each process. The arrays are then listed in a GUI (18). The GUI allows the designer to create memory resources, specifying the type of memory and packing mode. The designer is also provided with the ability to vary the format among a plurality of formats used to pack arrays to memory during the memory packing process. Upon completion of modifying the memory allocation, the designer saves the changes and such changes are effectuated by automatically updating the synthesis intermediate format.
    • 一种用于产生集成电路设计的行为综合工具(14)。 该工具允许设计者交互地(18)将变量或数组分配给存储器资源,而不必修改集成电路(12)的源代码描述(12)。 该工具读取源代码描述(12)并生成存储在存储器中的合成中间格式(16)。 该工具搜索内存中的合成格式,以查找每个进程的数组。 然后将数组列在GUI(18)中。 GUI允许设计人员创建内存资源,指定内存类型和打包模式。 在存储器打包过程中,设计者还具有在用于将阵列打包到存储器的多种格式之间改变格式的能力。 完成修改内存分配后,设计人员保存更改,并通过自动更新合成中间格式来实现这些更改。