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1. 发明申请

WO2008157154A1 METHOD AND APPARATUS FOR OPTIMIZING A GATE CHANNEL 审中-公开
标题翻译：优化门通道的方法和装置
公开(公告)号：WO2008157154A1
公开(公告)日：2008-12-24
申请号：PCT/US2008/066491
申请日：2008-06-11
申请人： TOKYO ELECTRON LIMITED , YAMASHITA, Asao , FUNK, Merritt , PRAGER, Daniel , CHEN, Lee , SUNDARARAJAN, Radha
发明人： YAMASHITA, Asao , FUNK, Merritt , PRAGER, Daniel , CHEN, Lee , SUNDARARAJAN, Radha
IPC分类号： G06F17/50
CPC分类号： H01L21/32137 , H01L21/28017 , H01L22/12 , H01L22/20 , H01L29/78 , H01L2924/0002 , H01L2924/00
摘要： The invention can provide a method of processing a substrate using Gate-Optimization processing sequences and evaluation libraries that can include gate-etch procedures, COR-etch procedures, and evaluation procedures
摘要翻译：本发明可以提供使用Gate-Optimization处理序列和评估库处理衬底的方法，所述评估库可以包括栅极蚀刻程序，COR蚀刻程序和评估程序

2. 发明申请

WO2007117738A2 DYNAMIC METROLOGY SAMPLING WITH WAFER UNIFORMITY CONTROL 审中-公开
标题翻译：动态计量采样与均匀控制
公开(公告)号：WO2007117738A2
公开(公告)日：2007-10-18
申请号：PCT/US2007060960
申请日：2007-01-24
申请人： TOKYO ELECTRON LTD , IBM , FUNK MERRITT , SUNDARARAJAN RADHA , PRAGER DANIEL , NATZLE WESLEY
发明人： FUNK MERRITT , SUNDARARAJAN RADHA , PRAGER DANIEL , NATZLE WESLEY
IPC分类号： G06K9/00
CPC分类号： G03F7/70625 , G03F7/70525
摘要： A method of processing a wafer is presented that includes creating a pre-processing measurement map using measured metrology data for the wafer including metrology data for at least one isolated structure on the wafer, metrology data for at least one nested structure on the wafer, or mask data. At least one pre-processing prediction map is calculated for the wafer. A pre- processing confidence map is calculated for the wafer. The pre-processing confidence map includes a set of confidence data for the plurality of dies on the wafer. A prioritized measurement site is determined when the confidence data for one or more dies is not within the confidence limits. A new measurement recipe that includes the prioritized measurement site is then created.
摘要翻译：提出了一种处理晶片的方法，其包括使用测量的用于晶片的测量数据创建预处理测量图，包括晶片上的至少一个隔离结构的测量数据，晶片上的至少一个嵌套结构的度量数据，或掩码数据。为晶片计算至少一个预处理预测图。为晶片计算预处理置信图。预处理置信图包括晶片上的多个管芯的一组置信数据。当一个或多个管芯的置信度数据不在置信限度内时，确定优先测量点。然后创建包含优先测量站点的新测量配方。

3. 发明申请

WO2007117737A2 DYNAMIC METROLOGY SAMPLING WITH WAFER UNIFORMITY CONTROL 审中-公开
标题翻译：动态计量采样与均匀控制
公开(公告)号：WO2007117737A2
公开(公告)日：2007-10-18
申请号：PCT/US2007/060953
申请日：2007-01-24
申请人： TOKYO ELECTRON LIMITED , INTERNATIONAL BUSINESS MACHINES CORPORATION ("IBM") , FUNK, Merritt , SUNDARARAJAN, Radha , PRAGER, Daniel , NATZLE, Wesley
发明人： FUNK, Merritt , SUNDARARAJAN, Radha , PRAGER, Daniel , NATZLE, Wesley
IPC分类号： H01L21/66
CPC分类号： H01L22/12
摘要： A method of processing a wafer is presented that includes creating a pre-processing measurement map using measured metrology data for the wafer including metrology data for at least one isolated structure on the wafer, metrology data for at least one nested structure on the wafer, bi-layer mask data, and BARC layer data. At least one pre-processing prediction map is calculated for the wafer. A pre-processing confidence map is calculated for the wafer. The pre-processing confidence map includes a set of confidence data for the plurality of dies on the wafer. A prioritized measurement site is determined when the confidence data for one or more dies is not within the confidence limits. A new measurement recipe that includes the prioritized measurement site is then created.
摘要翻译：提出了一种处理晶片的方法，其包括使用测量的晶片的测量数据创建预处理测量图，包括晶片上的至少一个隔离结构的测量数据，晶片上的至少一个嵌套结构的度量数据，bi 层掩模数据和BARC层数据。为晶片计算至少一个预处理预测图。计算晶片的预处理置信图。预处理置信图包括晶片上的多个管芯的一组置信数据。当一个或多个管芯的置信度数据不在置信限度内时，确定优先测量点。然后创建包含优先测量站点的新测量配方。

4. 发明申请

WO2007117737A3 DYNAMIC METROLOGY SAMPLING WITH WAFER UNIFORMITY CONTROL 审中-公开
标题翻译：动态计量采样与均匀控制
公开(公告)号：WO2007117737A3
公开(公告)日：2008-04-17
申请号：PCT/US2007060953
申请日：2007-01-24
申请人： TOKYO ELECTRON LTD , IBM , FUNK MERRITT , SUNDARARAJAN RADHA , PRAGER DANIEL , NATZLE WESLEY
发明人： FUNK MERRITT , SUNDARARAJAN RADHA , PRAGER DANIEL , NATZLE WESLEY
IPC分类号： G06F19/00
CPC分类号： H01L22/12
摘要： A method of processing a wafer is presented that includes creating a pre-processing measurement map using measured metrology data for the wafer including metrology data for at least one isolated structure on the wafer, metrology data for at least one nested structure on the wafer, bi-layer mask data, and BARC layer data. At least one pre-processing prediction map is calculated for the wafer. A pre-processing confidence map is calculated for the wafer. The pre-processing confidence map includes a set of confidence data for the plurality of dies on the wafer. A prioritized measurement site is determined when the confidence data for one or more dies is not within the confidence limits. A new measurement recipe that includes the prioritized measurement site is then created.
摘要翻译：提出了一种处理晶片的方法，其包括使用测量的晶片的测量数据创建预处理测量图，包括晶片上的至少一个隔离结构的测量数据，晶片上的至少一个嵌套结构的度量数据，bi 层掩模数据和BARC层数据。为晶片计算至少一个预处理预测图。计算晶片的预处理置信图。预处理置信图包括晶片上的多个管芯的一组置信数据。当一个或多个管芯的置信度数据不在置信限度内时，确定优先测量点。然后创建包含优先测量站点的新测量配方。

5. 发明申请

WO2006036245A2 ISO/NESTED CASCADING TRIM CONTROL WITH MODEL FEEDBACK UPDATES 审中-公开
标题翻译：采用模型反馈更新的ISO /嵌套式级联精度控制
公开(公告)号：WO2006036245A2
公开(公告)日：2006-04-06
申请号：PCT/US2005023580
申请日：2005-06-30
申请人： TOKYO ELECTRON LTD , YAMASHITA ASAO , FUNK MERRITT LANE , PRAGER DANIEL
发明人： YAMASHITA ASAO , FUNK MERRITT LANE , PRAGER DANIEL
IPC分类号： H01L21/66
CPC分类号： H01L22/20 , H01L21/32139 , H01L2924/0002 , H01L2924/00
摘要： This method includes a method for etch processing that allows the bias between isolated and nested structures/features to be adjusted, correcting for a process wherein the isolated structures/features need to be smaller than the nested structures/features and wherein the nested structures/features need to be reduced relative to the isolated structures/features, while allowing for the critical control of trimming.
摘要翻译：该方法包括用于蚀刻处理的方法，该方法允许调整隔离和嵌套结构/特征之间的偏置，校正其中隔离结构/特征需要小于嵌套结构/特征的过程，并且其中嵌套结构/特征需要相对于隔离的结构/特征来减小，同时允许对修剪的关键控制。

6. 发明申请

WO2008014548A1 ARGUMENT MAPPING SYSTEM 审中-公开
标题翻译： ARGUMENT映射系统
公开(公告)号：WO2008014548A1
公开(公告)日：2008-02-07
申请号：PCT/AU2007/001068
申请日：2007-08-01
申请人： AUSTHINK SOFTWARE PTY LTD , VAN GELDER, Timothy , BULKA, Andy , PRAGER, Daniel , SBARSKI, Peter , MARRIOTT, Kimbal, George
发明人： VAN GELDER, Timothy , BULKA, Andy , PRAGER, Daniel , SBARSKI, Peter , MARRIOTT, Kimbal, George
IPC分类号： G09B5/02 , G06F19/00
CPC分类号： G09B5/02
摘要： A method is disclosed for representing reasoning by means of a diagram. The diagram includes a plurality of boxes including first and second boxes located on a Cartesian plane. The first boxes do not include other boxes and correspond to propositions. The second boxes include one or more first boxes and correspond to reasons or objections. Boxes included in other boxes correspond to premises. A first box not included in a further box corresponds to a main conclusion of the reasoning. Directional paths connect second boxes to first boxes and correspond to relations of support or opposition between reasons and propositions. At least some first boxes may include associated first text for conveying meaning of an associated proposition. At least some second boxes include associated second text for conveying a nature of a relation of support or opposition. At least some second boxes may include an open boundary such that the or each path does not cross a visual line associated with the boundary.
摘要翻译：公开了一种通过图表示推理的方法。该图包括多个框，包括位于笛卡尔平面上的第一和第二框。第一个框不包括其他框并对应于命题。第二个框包括一个或多个第一个框，并对应于原因或异议。包括在其他箱子中的盒子对应于房屋。未包含在另一个框中的第一个框对应于推理的主要结论。定向路径将第二个盒子连接到第一个盒子，并对应于原因和命题之间的支持或反对关系。至少一些第一框可以包括用于传达相关命题的意义的相关联的第一文本。至少一些第二框包括用于传达支持或反对关系的性质的相关联的第二文本。至少一些第二框可以包括开放边界，使得该路线或每个路径不跨越与该边界相关联的视线。

7. 发明申请

WO2007117738A3 DYNAMIC METROLOGY SAMPLING WITH WAFER UNIFORMITY CONTROL 审中-公开
公开(公告)号：WO2007117738A3
公开(公告)日：2007-10-18
申请号：PCT/US2007/060960
申请日：2007-01-24
申请人： TOKYO ELECTRON LIMITED , INTERNATIONAL BUSINESS MACHINES CORPORATION , FUNK, Merritt , SUNDARARAJAN, Radha , PRAGER, Daniel , NATZLE, Wesley
发明人： FUNK, Merritt , SUNDARARAJAN, Radha , PRAGER, Daniel , NATZLE, Wesley
IPC分类号： G01R31/26
摘要： A method of processing a wafer is presented that includes creating a pre-processing measurement map using measured metrology data for the wafer including metrology data for at least one isolated structure on the wafer, metrology data for at least one nested structure on the wafer, or mask data. At least one pre-processing prediction map is calculated for the wafer. A pre- processing confidence map is calculated for the wafer. The pre-processing confidence map includes a set of confidence data for the plurality of dies on the wafer. A prioritized measurement site is determined when the confidence data for one or more dies is not within the confidence limits. A new measurement recipe that includes the prioritized measurement site is then created.

8. 发明申请

WO2006083919A1 ISO/NESTED CONTROL FOR SOFT MASK PROCESSING 审中-公开
标题翻译：用于软掩模加工的ISO / NESTED控制
公开(公告)号：WO2006083919A1
公开(公告)日：2006-08-10
申请号：PCT/US2006/003482
申请日：2006-02-01
申请人： TOKYO ELECTRON LIMITED , YAMASHITA, Asao , FUNK, Merritt , PRAGER, Daniel
发明人： YAMASHITA, Asao , FUNK, Merritt , PRAGER, Daniel
IPC分类号： H01L21/66
CPC分类号： H01L22/20 , H01L2924/0002 , H01L2924/00
摘要： This method includes a method for etch processing that allows the bias between isolated and nested structures/features to be adjusted, correcting for a process wherein the isolated structures/features need to be smaller than the nested structures/features and wherein the nested structures/features need to be reduced relative to the isolated structures/features, while allowing for the critical control of trimming.
摘要翻译：该方法包括用于蚀刻处理的方法，其允许调整隔离结构/嵌套结构/特征之间的偏置，校正其中隔离结构/特征需要小于嵌套结构/特征的过程，并且其中嵌套结构/特征需要相对于孤立的结构/特征而减少，同时允许对修剪的关键控制。

9. 发明申请

WO2012135531A1 CONTACT PROCESSING USING MULTI-INPUT/MULTI-OUTPUT (MIMO) MODELS 审中-公开
标题翻译：使用多输入/多输出（MIMO）模型的接触处理
公开(公告)号：WO2012135531A1
公开(公告)日：2012-10-04
申请号：PCT/US2012/031271
申请日：2012-03-29
申请人： TOKYO ELECTRON LIMITED , PRAGER, Daniel, J. , FUNK, Merritt , BIOLSI, Peter , SHIMIZU, Ryukichi
发明人： PRAGER, Daniel, J. , FUNK, Merritt , BIOLSI, Peter , SHIMIZU, Ryukichi
IPC分类号： G01K1/08
CPC分类号： H01L22/20 , H01J37/32082 , H01J37/3266 , H01L21/31116 , H01L21/823871 , H01L22/12 , H01L2924/0002 , H01L2924/00
摘要： The invention provides a systems and methods for creating Double Pattern (DP) structures on a patterned wafer in real-time using Dual Pattern Contact-Etch (DPCE) processing sequences and associated Contact-Etch- Multi-Input/Multi-Output (CE-MIMO) models. The DPCE processing sequences can include one or more contact-etch procedures, one or more measurement procedures, one or more contact-etch modeling procedures, and one or more contact-etch verification procedures. The CE-MIMO model uses dynamically interacting behavioral modeling between multiple layers and/or multiple contact-etch procedures. The multiple layers and/or the multiple contact-etch procedures can be associated with the creation of lines, trenches, vias, spacers, contacts, and gate structures that can be created during Double Patterning (DP) procedures.
摘要翻译：本发明提供了一种用于在图案化晶片上实时使用双模式接触蚀刻（DPCE）处理序列和相关联的接触蚀刻多输入/多输出（CE- MIMO）模型。 DPCE处理序列可以包括一个或多个接触蚀刻程序，一个或多个测量程序，一个或多个接触蚀刻建模程序以及一个或多个接触蚀刻验证程序。 CE-MIMO模型使用多层和/或多个接触蚀刻程序之间的动态交互行为建模。多层和/或多层接触蚀刻程序可以与在双重图案化（DP）程序期间创建的线，沟槽，通孔，间隔物，接触和门结构的创建相关联。

10. 发明申请

WO2008157156A1 METHOD AND APPARATUS FOR CREATING A GATE OPTIMIZATION EVALUATION LIBRARY 审中-公开
标题翻译：用于创建门优化评估库的方法和装置
公开(公告)号：WO2008157156A1
公开(公告)日：2008-12-24
申请号：PCT/US2008/066494
申请日：2008-06-11
申请人： TOKYO ELECTRON LIMITED , YAMASHITA, Asao , FUNK, Merritt , PRAGER, Daniel , CHEN, Lee , SUNDARARAJAN, Radha
发明人： YAMASHITA, Asao , FUNK, Merritt , PRAGER, Daniel , CHEN, Lee , SUNDARARAJAN, Radha
IPC分类号： G06F15/00
CPC分类号： H01L22/12 , G06F17/5036 , H01L21/67253 , H01L2924/0002 , H01L2924/00
摘要： The invention can provide a method of processing a substrate using Gate-Optimization processing sequences and evaluation libraries that can include gate-etch procedures, COR-etch procedures, and evaluation procedures
摘要翻译：本发明可以提供使用Gate-Optimization处理序列和评估库处理衬底的方法，其可以包括栅极蚀刻程序，COR蚀刻程序和评估程序

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