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1. 发明申请

WO2008035317A3 A MICROPROCESSOR HAVING AT LEAST ONE APPLICATION SPECIFIC FUNCTIONAL UNIT AND METHOD TO DESIGN SAME 审中-公开
标题翻译：具有至少一个应用程序特定功能单元的微处理器和设计相同的方法
公开(公告)号：WO2008035317A3
公开(公告)日：2008-10-23
申请号：PCT/IB2007053866
申请日：2007-09-24
申请人： ECOLE POLYTECH , POZZI LAURA , IENNE PAOLO
发明人： POZZI LAURA , IENNE PAOLO
IPC分类号： G06F9/38 , G06F9/45 , G06F15/78 , G06F17/50
CPC分类号： G06F9/3875 , G06F8/447 , G06F9/3897 , G06F17/505
摘要： Customisable embedded processors that are available on the market make it possible for designers to speed up execution of applications by using Application-specific Functional Units (AFUs), implementing Instruction-Set Extensions (ISEs). Furthermore, techniques for automatic ISE identification have been improving; many algorithms have been proposed for choosing, given the application's source code, the best ISEs under various constraints. Read and write ports between the AFUs and the processor register file are an expensive asset, fixed in the micro-architecture - some processors indeed only allow two read ports and one write port - and yet, on the other hand, a large availability of inputs and outputs to and from the AFUs exposes high speedup. Here we present a solution to the limitation of actual register file ports by serialising register file access and therefore addressing multi-cycle read and write. It does so in an innovative way for two reasons: (1) it exploits and brings forward the progress in ISE identification under constraint, and (2) it combines register file access serialisation with pipelining in order to obtain the best global solution. Our method consists of scheduling graphs - corresponding to ISEs - under input/ output constraint
摘要翻译：市场上可定制的嵌入式处理器使设计人员能够通过使用专用功能单元（AFU），实现指令集扩展（ISE）来加速应用程序的执行。此外，自动识别ISE的技术也在不断改进。已经提出了许多算法来选择在给定应用的源代码的情况下在各种约束下的最佳ISE。 AFU和处理器寄存器文件之间的读写端口是一项昂贵的资产，固定在微架构中 - 某些处理器实际上只允许两个读端口和一个写端口 - 但另一方面却有大量的输入并且AFU的输出可以高速加速。在这里，我们通过串行化寄存器文件访问来解决实际寄存器文件端口的限制，并因此解决了多周期读取和写入问题。它以一种创新的方式做到了这一点，原因有二：（1）它利用并提出了约束条件下ISE识别的进展;（2）它将寄存器文件访问序列化和流水线结合起来，以获得最佳的全局解决方案。我们的方法由在输入/输出约束下的调度图 - 对应于ISE组成

2. 发明申请

WO2008035317A2 A MICROPROCESSOR HAVING AT LEAST ONE APPLICATION SPECIFIC FUNCTIONAL UNIT AND METHOD TO DESIGN SAME 审中-公开
标题翻译：具有至少一个应用特定功能单元的微处理器及其设计方法
公开(公告)号：WO2008035317A2
公开(公告)日：2008-03-27
申请号：PCT/IB2007/053866
申请日：2007-09-24
申请人： ECOLE POLYTECHNIQUE FEDERALE DE LAUSANNE (EPFL) , POZZI, Laura , IENNE, Paolo
发明人： POZZI, Laura , IENNE, Paolo
CPC分类号： G06F9/3875 , G06F8/447 , G06F9/3897 , G06F17/505
摘要： Customisable embedded processors that are available on the market make it possible for designers to speed up execution of applications by using Application-specific Functional Units (AFUs), implementing Instruction-Set Extensions (ISEs). Furthermore, techniques for automatic ISE identification have been improving; many algorithms have been proposed for choosing, given the application's source code, the best ISEs under various constraints. Read and write ports between the AFUs and the processor register file are an expensive asset, fixed in the micro-architecture - some processors indeed only allow two read ports and one write port - and yet, on the other hand, a large availability of inputs and outputs to and from the AFUs exposes high speedup. Here we present a solution to the limitation of actual register file ports by serialising register file access and therefore addressing multi-cycle read and write. It does so in an innovative way for two reasons: (1) it exploits and brings forward the progress in ISE identification under constraint, and (2) it combines register file access serialisation with pipelining in order to obtain the best global solution. Our method consists of scheduling graphs - corresponding to ISEs - under input/ output constraint
摘要翻译：市场上可用的可定制的嵌入式处理器使设计人员能够通过使用特定于应用的功能单元（AFU），实现指令集扩展（ISE）来加快应用程序的执行。此外，用于自动ISE识别的技术已经改进; 考虑到应用程序的源代码，已经提出了许多算法来选择在各种约束条件下最好的ISE。 AFU和处理器寄存器文件之间的读写端口是一种昂贵的资产，固定在微架构中 - 一些处理器确实只允许两个读端口和一个写端口，另一方面，输入的可用性很大并且从AFU输出到高加速度。在这里，我们提出了通过串行化寄存器文件访问来限制实际寄存器文件端口的解决方案，因此寻址多周期读写。它以创新的方式做到这一点有两个原因：（1）利用并提出了ISE识别在约束条件下的进展，（2）将注册文件访问序列化与流水线结合在一起，以获得最佳的全局解决方案。我们的方法包括在输入/输出约束下调度与ISE对应的图

3. 发明申请

WO2005103904A1 VIRTUAL MEMORY WINDOW WITH DYNAMIC PREFETCHING SUPPORT 审中-公开
标题翻译：具有动态预取支持的虚拟存储窗口
公开(公告)号：WO2005103904A1
公开(公告)日：2005-11-03
申请号：PCT/EP2005/051730
申请日：2005-04-19
申请人： ECOLE POLYTECHNIQUE FEDERALE DE LAUSANNE (EPFL) , VULETIC, Miljan , POZZI, Laura , IENNE, Paolo
发明人： VULETIC, Miljan , POZZI, Laura , IENNE, Paolo
IPC分类号： G06F12/10
CPC分类号： G06F12/1081 , G06F9/3877
摘要： Reconfgurable Systems-an-Chip (RSoCs) on the market consist of full-fledged processors and large Field-Programmable Gate Arrays (FPGAs). The latter can be used to implement the system glue logic, various peripherals, and applicationspecific coprocessors. Using FPGAs for application-specific coprocessors has certain speedup potentials, but it is less present in practice because of the complexity of interfacing the software application with the coprocessor. In the present application, we present a virtualisation layer consisting of an operatingsystem extension and a hardware component. It lowers the complexity of interfacing and increases portability potentials, while it also allows the coprocessor to access the user virtual memory through a virtual memory window. The burden of moving data between processor and coprocessor is shifted from the programmer to the operating system.
摘要翻译：市场上可重构的系统芯片（RSoC）由完整的处理器和大型现场可编程门阵列（FPGA）组成。后者可用于实现系统胶合逻辑，各种外设和应用程序特定的协处理器。对于特定于应用程序的协处理器使用FPGA具有一定的加速电位，但由于将软件应用与协处理器连接的复杂性在实践中较少存在。在本应用中，我们提出了一个由操作系统扩展和硬件组件组成的虚拟化层。它降低了接口的复杂性并增加了可移植性的潜力，同时它还允许协处理器通过虚拟存储器窗口访问用户虚拟内存。在处理器和协处理器之间移动数据的负担从编程器转移到操作系统。

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