专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

WO2005104027A2 DATA PROCESSING APPARATUS THAT PROVIDES PARALLEL ACCESS TO MULTI-DIMENSIONAL ARRAY OF DATA VALUES 审中-公开
标题翻译：数据处理设备提供并行访问数据值的多维阵列
公开(公告)号：WO2005104027A2
公开(公告)日：2005-11-03
申请号：PCT/IB2005/051308
申请日：2005-04-21
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , SETHURAMAN, Ramanathan , BERIC, Aleksandar , ALBA PINTO, Carlos, A. , PETERS, Harm, J., A., M. , MEUWISSEN, Patrick, P., E. , SRINIVASAN, Balakrishnan , VELDMAN, Gerard
发明人： SETHURAMAN, Ramanathan , BERIC, Aleksandar , ALBA PINTO, Carlos, A. , PETERS, Harm, J., A., M. , MEUWISSEN, Patrick, P., E. , SRINIVASAN, Balakrishnan , VELDMAN, Gerard
IPC分类号： G06N3/063
CPC分类号： H04N19/433 , G06F12/00
摘要： An array of data values, such as an image of pixel values, is stored in a main memory (12). A processing operation is performed using the pixel values. The processing operation defines time points of movement of a multidimensional region (20, 22) of locations in the image. Pixel values from inside and around the region are cached for processing. At least when a cache miss occurs for a pixel value from outside the region, cache replacement of data in cache locations (142) is performed. Locations that store pixel data for locations in the image outside the region (20, 22) are selected for replacement, selectively exempting from replacement cache locations (142) that store pixel data locations in the image inside the region. In embodiments, different types of cache structure are used for caching data values inside and outside the region. In an embodiment the cache locations for pixel data inside the regions support a higher level of output parallelism than the cache locations for pixel data around the region. In a further embodiment the cache for locations inside the region contains sets of banks, each set for a respective line from the image, data from the lines being distributed in a cyclically repeating fashion over the banks.
摘要翻译：诸如像素值的图像的数据值阵列存储在主存储器（12）中。使用像素值执行处理操作。处理操作定义图像中位置的多维区域（20,22）的移动时间点。内部和周围区域的像素值被缓存进行处理。至少当从区域外的像素值发生高速缓存未命中时，执行高速缓存位置（142）中的数据的高速缓存替换。选择存储用于区域（20,22）以外的图像中的位置的像素数据的位置用于替换，以选择性地免除存储区域内的图像中的像素数据位置的替换高速缓存位置（142）。在实施例中，不同类型的高速缓存结构被用于缓存区域内外的数据值。在一个实施例中，区域内的像素数据的高速缓存位置支持比围绕该区域的像素数据的高速缓存位置更高级的输出并行性。在另一实施例中，区域内的高速缓冲存储器包含一组存储体，每个存储体集合针对来自图像的相应行设置，来自行的数据以循环重复的方式分布在存储体上。

2. 发明申请

WO2005116925A2 METHOD FOR ELECTRONIC IMAGE PROCESSING 审中-公开
标题翻译：电子图像处理方法
公开(公告)号：WO2005116925A2
公开(公告)日：2005-12-08
申请号：PCT/IB2005051682
申请日：2005-05-24
申请人： KONINKL PHILIPS ELECTRONICS NV , MEUWISSEN PATRICK P E , SETHURAMAN RAMANATHAN , PETERS HARM J A M , ERNST FABIAN E
发明人： MEUWISSEN PATRICK P E , SETHURAMAN RAMANATHAN , PETERS HARM J A M , ERNST FABIAN E
IPC分类号： G06T5/00 , G06T5/20 , G06T7/00 , G06T7/20
CPC分类号： G06T5/20 , G06T7/11 , G06T7/20 , G06T2207/10016
摘要： A method for electronic image processing wherein a calculation is performed on groups of pixels. Each group comprises a center pixel (21) and a group of surrounding pixels. The calculation is performed on a number of center pixels in parallel, a group of displacement vectors is associated with each centre pixel, and during each step of the calculation for the number of pixels a same displacement vector ((-2,-2);(-2,-1)) is used, wherein for each of the displacement vectors for each of the center pixels a function value is calculated and the displacement vectors are processed sequentially within the group of displacement vectors. Preferably use is made of a footprint cache wherein for each pixel the results of calculations are stored. Preferably the displacement vectors are dealt with line-byline.
摘要翻译：一种用于电子图像处理的方法，其中对像素组执行计算。每个组包括中心像素（21）和一组周围像素。对多个中心像素并行执行计算，一组位移矢量与每个中心像素相关联，并且在计算相同位移矢量（（-2，-2）的像素数的每个步骤期间）（-2，-1）），其中对于每个中心像素的每个位移矢量，计算功能值，并且在位移矢量组内顺序地处理位移矢量。优选使用足迹缓存，其中对于每个像素，存储计算结果。优选地，逐行处理位移矢量。

3. 发明申请

WO2004034253A2 DATA PROCESSING APPARATUS ADDRESS RANGE DEPENDENT PARALLELIZATION OF INSTRUCTIONS 审中-公开
标题翻译：数据处理设备地址范围依赖于指令的并行
公开(公告)号：WO2004034253A2
公开(公告)日：2004-04-22
申请号：PCT/IB2003/004327
申请日：2003-10-01
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , SETHURAMAN, Ramanathan , SRINIVASAN, Balakrishnan , ALBA PINTO, Carlos, A. , PETERS, Harm, J., A., M. , PESET LLOPIS, Rafael
发明人： SETHURAMAN, Ramanathan , SRINIVASAN, Balakrishnan , ALBA PINTO, Carlos, A. , PETERS, Harm, J., A., M. , PESET LLOPIS, Rafael
IPC分类号： G06F9/38
CPC分类号： G06F9/30003 , G06F9/30149 , G06F9/3802 , G06F9/3853
摘要： A data processing apparatus has an instruction memory system arranged to output an instruction word addressed by an instruction address. An instruction execution unit, processes a plurality of instructions from the instruction word in parallel. A detection unit, detects in which of a plurality of ranges the instruction address lies. The detection unit is coupled to the instruction execution unit and/or the instruction memory system, to control a way in which the instruction execution unit parallelizes processing of the instructions from the instruction word, dependent on a detected range. In an embodiment the instruction execution unit and/or the instruction memory system adjusts a width of the instruction word that determines a number of instructions from the instruction word that is processed in parallel, dependent on the detected range.
摘要翻译：数据处理装置具有布置成输出由指令地址寻址的指令字的指令存储器系统。指令执行单元，并行地从指令字处理多个指令。检测单元，检测指示地址所在的多个范围中的哪一个。检测单元耦合到指令执行单元和/或指令存储器系统，以根据检测到的范围来控制指令执行单元将来自指令字的指令的处理并行化的方式。在一个实施例中，指令执行单元和/或指令存储器系统根据检测到的范围来调整从并行处理的指令字确定指令字数的指令字的宽度。

4. 发明申请

WO2005104027A3 DATA PROCESSING APPARATUS THAT PROVIDES PARALLEL ACCESS TO MULTI-DIMENSIONAL ARRAY OF DATA VALUES 审中-公开
标题翻译：数据处理设备提供并行访问数据值的多维阵列
公开(公告)号：WO2005104027A3
公开(公告)日：2006-03-02
申请号：PCT/IB2005051308
申请日：2005-04-21
申请人： KONINKL PHILIPS ELECTRONICS NV , SETHURAMAN RAMANATHAN , BERIC ALEKSANDAR , ALBA PINTO CARLOS A , PETERS HARM J A M , MEUWISSEN PATRICK P E , SRINIVASAN BALAKRISHNAN , VELDMAN GERARD
发明人： SETHURAMAN RAMANATHAN , BERIC ALEKSANDAR , ALBA PINTO CARLOS A , PETERS HARM J A M , MEUWISSEN PATRICK P E , SRINIVASAN BALAKRISHNAN , VELDMAN GERARD
IPC分类号： H04N7/26
CPC分类号： H04N19/433
摘要： An array of data values, such as an image of pixel values, is stored in a main memory (12). A processing operation is performed using the pixel values. The processing operation defines time points of movement of a multidimensional region (20, 22) of locations in the image. Pixel values from inside and around the region are cached for processing. At least when a cache miss occurs for a pixel value from outside the region, cache replacement of data in cache locations (142) is performed. Locations that store pixel data for locations in the image outside the region (20, 22) are selected for replacement, selectively exempting from replacement cache locations (142) that store pixel data locations in the image inside the region. In embodiments, different types of cache structure are used for caching data values inside and outside the region. In an embodiment the cache locations for pixel data inside the regions support a higher level of output parallelism than the cache locations for pixel data around the region. In a further embodiment the cache for locations inside the region contains sets of banks, each set for a respective line from the image, data from the lines being distributed in a cyclically repeating fashion over the banks.
摘要翻译：诸如像素值的图像的数据值阵列存储在主存储器（12）中。使用像素值执行处理操作。处理操作定义图像中位置的多维区域（20,22）的移动时间点。内部和周围区域的像素值被缓存进行处理。至少当从区域外的像素值发生高速缓存未命中时，执行高速缓存位置（142）中的数据的高速缓存替换。选择存储用于区域（20,22）以外的图像中的位置的像素数据的位置用于替换，以选择性地免除存储区域内的图像中的像素数据位置的替换高速缓存位置（142）。在实施例中，不同类型的高速缓存结构被用于缓存区域内外的数据值。在一个实施例中，区域内的像素数据的高速缓存位置支持比围绕该区域的像素数据的高速缓存位置更高级的输出并行性。在另一实施例中，区域内的高速缓冲存储器包含一组存储体，每个存储体集合针对来自图像的相应行设置，来自行的数据以循环重复的方式分布在存储体上。

5. 发明申请

WO2004059468A3 VERY LONG INSTRUCTION WORD PROCESSOR 审中-公开
标题翻译：很长的指导字处理器
公开(公告)号：WO2004059468A3
公开(公告)日：2004-10-28
申请号：PCT/IB0305695
申请日：2003-12-03
申请人： KONINKL PHILIPS ELECTRONICS NV , SRINIVASAN BALAKRISHNAN , SETHURAMAN RAMANATHAN , ALBA PINTO CARLOS A , PETERS HARM J A M , PESET LLOPIS RAFAEL
发明人： SRINIVASAN BALAKRISHNAN , SETHURAMAN RAMANATHAN , ALBA PINTO CARLOS A , PETERS HARM J A M , PESET LLOPIS RAFAEL
IPC分类号： G06F9/38
CPC分类号： G06F9/3885 , G06F9/3853
摘要： The invention relates to a very long instruction word (VLIW) processor comprising a plurality of functional units (110, 130, 135), each for executing an operation, and a VLIW controller (100) connected to each of said functional units (110, 130, 135) and adapted to controlling said functional units (110, 130, 135). The VLIW processor comprises at least one indication means (140) associated with one of said functional units (135) and adapted to registering and indicating to the VLIW controller (100) whether said one functional unit (135) is idle or operating.
摘要翻译：本发明涉及包括多个用于执行操作的功能单元（110,130,135）的超长指令字（VLIW）处理器，以及连接到每个所述功能单元（110,130,135）的VLIW控制器（100）并且适于控制所述功能单元（110,130,135）。 VLIW处理器包括至少一个与所述功能单元（135）中的一个相关联的指示装置（140），并且适于向VLIW控制器（100）注册并向VLIW控制器（100）指示所述一个功能单元（135）是空闲还是操作。

6. 发明申请

WO2004034253A3 VLIW PROCESSOR WITH VARIABLE, ADDRESS RANGE DEPENDENT ISSUE-WIDTH 审中-公开
标题翻译： VLIW处理器具有可变的，地址范围相关的问题宽度
公开(公告)号：WO2004034253A3
公开(公告)日：2004-10-28
申请号：PCT/IB0304327
申请日：2003-10-01
申请人： KONINKL PHILIPS ELECTRONICS NV , SETHURAMAN RAMANATHAN , SRINIVASAN BALAKRISHNAN , ALBA PINTO CARLOS A , PETERS HARM J A M , PESET LLOPIS RAFAEL
发明人： SETHURAMAN RAMANATHAN , SRINIVASAN BALAKRISHNAN , ALBA PINTO CARLOS A , PETERS HARM J A M , PESET LLOPIS RAFAEL
IPC分类号： G06F9/30 , G06F9/38
CPC分类号： G06F9/30003 , G06F9/30149 , G06F9/3802 , G06F9/3853
摘要： A data processing apparatus has an instruction memory system arranged to output an instruction word addressed by an instruction address. An instruction execution unit, processes a plurality of instructions from the instruction word in parallel. A detection unit, detects in which of a plurality of ranges the instruction address lies. The detection unit is coupled to the instruction execution unit and/or the instruction memory system, to control a way in which the instruction execution unit parallelizes processing of the instructions from the instruction word, dependent on a detected range. In an embodiment the instruction execution unit and/or the instruction memory system adjusts a width of the instruction word that determines a number of instructions from the instruction word that is processed in parallel, dependent on the detected range.
摘要翻译：数据处理装置具有布置成输出由指令地址寻址的指令字的指令存储器系统。指令执行单元，并行地从指令字处理多个指令。检测单元，检测指示地址所在的多个范围中的哪一个。检测单元耦合到指令执行单元和/或指令存储器系统，以根据检测到的范围来控制指令执行单元将来自指令字的指令的处理并行化的方式。在一个实施例中，指令执行单元和/或指令存储器系统根据检测到的范围来调整从并行处理的指令字确定指令字数的指令字的宽度。

7. 发明申请

WO2004034252A3 VLIW PROCESSOR WITH INSTRUCTION ADDRESS MODIFICATION 审中-公开
标题翻译：具有指令地址修改的VLIW处理器
公开(公告)号：WO2004034252A3
公开(公告)日：2004-10-21
申请号：PCT/IB0304184
申请日：2003-09-17
申请人： KONINKL PHILIPS ELECTRONICS NV , ALBA PINTO CARLOS A , SETHURAMAN RAMANATHAN , SRINIVASAN BALAKRISHNAN , PETERS HARM J A M , PESET LLOPIS RAFAEL
发明人： ALBA PINTO CARLOS A , SETHURAMAN RAMANATHAN , SRINIVASAN BALAKRISHNAN , PETERS HARM J A M , PESET LLOPIS RAFAEL
IPC分类号： G06F9/30 , G06F9/32 , G06F9/38
CPC分类号： G06F9/3802 , G06F9/3853
摘要： A program of instruction words is executed with a VLIW data processing apparatus. The apparatus comprises a plurality of functional units capable of executing a plurality of instructions from each instruction word in parallel. The instructions from each of at least some of the instruction words are fetched from respective memory units in parallel, addressed with an instruction address that is common for the functional units. Translation of the instruction address into a physical address can be modified for one or more particular ones of the memory units. Modification is controlled by modification update instructions in the program. Thus, it can be selected dependent on program execution which instructions from the memory units will be combined into the instruction word in response to the instruction address.
摘要翻译：用VLIW数据处理装置执行指令字的程序。该装置包括能够并行地从每个指令字执行多个指令的多个功能单元。来自各个指令字中的至少一些的指令被并行地从相应的存储器单元中取出，用功能单元共用的指令地址寻址。将指令地址转换为物理地址可以针对一个或多个特定存储器单元进行修改。修改由程序中的修改更新指令控制。因此，可以根据程序执行来选择来自存储器单元的指令将响应于指令地址而组合到指令字中。

8. 发明申请

WO2004059468A2 VERY LONG INSTRUCTION WORD PROCESSOR 审中-公开
标题翻译：非常长的指令词处理器
公开(公告)号：WO2004059468A2
公开(公告)日：2004-07-15
申请号：PCT/IB2003/005695
申请日：2003-12-03
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , SRINIVASAN, Balakrishnan , SETHURAMAN, Ramanathan , ALBA PINTO, Carlos, A. , PETERS, Harm, J., A., M. , PESET LLOPIS, Rafael
发明人： SRINIVASAN, Balakrishnan , SETHURAMAN, Ramanathan , ALBA PINTO, Carlos, A. , PETERS, Harm, J., A., M. , PESET LLOPIS, Rafael
IPC分类号： G06F9/38
CPC分类号： G06F9/3885 , G06F9/3853
摘要： The invention relates to a very long instruction word (VLIW) processor comprising a plurality of functional units (110, 130, 135), each for executing an operation, and a VLIW controller (100) connected to each of said functional units (110, 130, 135) and adapted to controlling said functional units (110, 130, 135). The VLIW processor comprises at least one indication means (140) associated with one of said functional units (135) and adapted to registering and indicating to the VLIW controller (100) whether said one functional unit (135) is idle or operating.
摘要翻译：本发明涉及一种非常长的指令字（VLIW）处理器，它包括多个用于执行操作的功能单元（110,130,135），和连接到每个所述功能单元（110,130,135）的VLIW控制器（100） 130,135），并适于控制所述功能单元（110,130,135）。所述VLIW处理器包括与所述功能单元（135）之一相关联的至少一个指示装置（140），并且适于向VLIW控制器（100）注册和指示所述一个功能单元（135）是空闲还是操作。

9. 发明申请

WO2004057460A2 SEGMENT-BASED MOTION ESTIMATION 审中-公开
标题翻译：基于分段的运动估计
公开(公告)号：WO2004057460A2
公开(公告)日：2004-07-08
申请号：PCT/IB2003/005474
申请日：2003-11-20
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , SETHURAMAN, Ramanathan , ERNST, Fabian, E. , MEUWISSEN, Patrick, P., E. , PETERS, Harm, J., A., M. , PESET LLOPIS, Rafael
发明人： SETHURAMAN, Ramanathan , ERNST, Fabian, E. , MEUWISSEN, Patrick, P., E. , PETERS, Harm, J., A., M. , PESET LLOPIS, Rafael
IPC分类号： G06F7/00
CPC分类号： G06T7/20 , G06T7/223 , H04N19/20 , H04N19/51
摘要： A method to determine motion vectors for respective segments (S11-S14) of a segmented image (100) comprises: creating sets of candidate motion vectors for the respective segments (S11-S14); dividing the segmented image (100) into a grid of blocks (b11-b88) of pixels; determining for the blocks (b11-b88) of pixels which of the candidate motion vectors belong to the blocks (b11-b88), on basis of the segments (S11-S14) and the locations of the blocks (b11-b88) within the segmented image (100); computing partial match errors for the blocks (b11-b88) on basis of the determined candidate motion vectors and on basis of pixel values of a further image (102); combining the partial match errors into a number of match errors per segment; selecting for each of the sets of candidate motion vectors respective candidate motion vectors on basis of the match errors; and assigning the selected candidate motion vectors as the motion vectors for the respective segments (S11-S14).
摘要翻译：确定分段图像（100）的各个分段（S11-S14）的运动矢量的方法包括：为各个分段创建多组候选运动矢量（S11-S14）; 将分割图像（100）分割成像素块（b11-b88）的网格; 基于区段（S11-S14）和区块（b11-b88）中的区块（b11-b88）的位置，确定像素的块（b11-b88）中的哪些候选运动矢量属于区块分段图像（100）; 基于所确定的候选运动向量并基于另一图像（102）的像素值计算块（b11-b88）的部分匹配误差; 将部分匹配错误组合成每段的大量匹配错误; 基于匹配误差为候选运动矢量的集合中的每一个选择相应的候选运动矢量; 并将所选择的候选运动矢量分配为各个段的运动矢量（S11-S14）。

10. 发明申请

WO2004034251A1 VLIW PROCESSOR WITH POWER SAVING 审中-公开
标题翻译：具有省电功能的VLIW处理器
公开(公告)号：WO2004034251A1
公开(公告)日：2004-04-22
申请号：PCT/IB2003/004183
申请日：2003-09-17
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , ALBA PINTO, Carlos, A. , SETHURAMAN, Ramanathan , SRINIVASAN, Balakrishnan , PETERS, Harm, J., A., M. , PESET LLOPIS, Rafael
发明人： ALBA PINTO, Carlos, A. , SETHURAMAN, Ramanathan , SRINIVASAN, Balakrishnan , PETERS, Harm, J., A., M. , PESET LLOPIS, Rafael
IPC分类号： G06F9/38
CPC分类号： G06F9/3853 , G06F1/3203 , G06F1/3237 , G06F1/3275 , G06F1/3287 , G06F9/3012 , G06F9/30141 , G06F9/30167 , G06F9/3869 , G06F9/3885 , Y02D10/128 , Y02D10/14 , Y02D10/171 , Y02D50/20
摘要： A data processing apparatus has an instruction memory system arranged to output an instruction word, capable of containing a plurality of instructions, respective instruction words being output in response to respective instruction addresses. An instruction execution unit contains a plurality of functional units, each capable of executing a respective instruction from the instruction word in parallel with execution of other instructions from the instruction word by other ones of the functional units. A power saving circuit is provided to switch a selectable subset of the functional units and/or parts of the instruction memory to a power saving state, while other functional units and parts of the instruction memory continue processing instructions in a normal power consuming state. The power saving circuit selects the functional units and/or parts of the instruction memory dependent on program execution.
摘要翻译：数据处理装置具有指令存储器系统，其被布置为输出能够包含多个指令的指令字，响应于相应的指令地址输出相应的指令字。指令执行单元包含多个功能单元，每个功能单元能够执行来自指令字的相应指令，并且与其他功能单元从指令字执行其他指令并行执行。提供省电电路以将功能单元和/或指令存储器的可选择子集切换到省电状态，而指令存储器的其他功能单元和部分在正常功耗状态下继续处理指令。省电电路根据程序执行选择指令存储器的功能单元和/或部分。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式