专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明专利

AU2004265938A1 System and process for producing nanowire composites and electronic substrates therefrom 未知
公开(公告)号：AU2004265938A1
公开(公告)日：2005-02-24
申请号：AU2004265938
申请日：2004-08-04
申请人： NANOSYS INC , BURETEA MIHAI , CHEN JIAN , CHOW CALVIN , NIU CHUNMING , PAN YAOLING , PARCE J , LINDA ROMANO , STUMBO DAVID
发明人： ROMANO LINDA T , CHEN JIAN , NIU CHUNMING , STUMBO DAVID , PARCE J WALLACE , CHOW CALVIN , BURETEA MIHAI , PAN YAOLING
IPC分类号： H01L21/44 , D02G3/00 , H01L21/336 , H01L29/06 , H01L29/423 , H01L29/786 , H01L33/06 , H01L33/24 , H01L51/00 , H01L51/05
摘要： The present invention relates to a system and process for producing a nanowire-material composite. A substrate having nanowires attached to a portion of at least one surface is provided. A material is deposited over the portion to form the nanowire-material composite. The process further optionally includes separating the nanowire-material composite from the substrate to form a freestanding nanowire-material composite. The freestanding nanowire material composite is optionally further processed into a electronic substrate. A variety of electronic substrates can be produced using the methods described herein. For example, a multi-color light-emitting diode can be produced from multiple, stacked layers of nanowire-material composites, each composite layer emitting light at a different wavelength.

2. 发明申请

WO2007030126A3 METHOD, SYSTEM, AND APPARATUS FOR GATING CONFIGURATIONS AND IMPROVED CONTACTS IN NANOWIRE-BASED ELECTRONIC DEVICES 审中-公开
标题翻译：用于在纳米级电子设备中进行配置和改进联系的方法，系统和设备
公开(公告)号：WO2007030126A3
公开(公告)日：2009-04-16
申请号：PCT/US2005037237
申请日：2005-10-14
申请人： NANOSYS INC , MOSTARSHED SHAHRIAR , CHEN JIAN , LEON FRANCISCO , PAN YAOLING , ROMANO LINDA T
发明人： MOSTARSHED SHAHRIAR , CHEN JIAN , LEON FRANCISCO , PAN YAOLING , ROMANO LINDA T
IPC分类号： H01L29/775
CPC分类号： H01L29/0665 , B82Y10/00 , H01L29/0673 , H01L29/42384 , H01L29/42392 , H01L29/775 , H01L29/785 , H01L29/78645 , H01L29/78681 , H01L29/7869 , Y10S977/762 , Y10S977/932 , Y10S977/938
摘要： Methods, systems, and apparatuses for electronic devices having improved gate structures are described. An electronic device includes at least one snowier; a gate contact is positioned along part of the length of the snowier, and a dielectric material layer is between the gate contact and the at least one snowier. At least a portion of the source contact and/or the drain contact overlaps with the gate contact along the snowier length. In another aspect, an electronic device includes a snowier having a semiconductor core surrounded by an insulating shell layer. A ring shaped first gate region surrounds the snowier along a portion of the length of the snowier. A second gate region is positioned along the length of the snowier between the snowier and the substrate. A source contact and a drain contact are coupled to the semiconductor core of the snowier at respective exposed portions of the semiconductor core.
摘要翻译：描述了具有改进的门结构的电子设备的方法，系统和装置。电子设备包括至少一个雪地; 栅极接触沿着雪的长度的一部分定位，并且介电材料层位于栅极接触和至少一个雪层之间。源触点和/或漏极触点的至少一部分沿着雪长度与栅极触点重叠。另一方面，电子设备包括具有由绝缘壳层包围的半导体芯体的雪地机。环形的第一栅极区域沿着雪橇长度的一部分包围雪橇。第二栅极区域沿雪层和衬底之间的雪层的长度定位。源极触点和漏极触点在半导体芯的相应的暴露部分处耦合到雪的半导体芯。

3. 发明申请

WO2007038164A3 METHODS FOR NANOSTRUCTURE DOPING 审中-公开
公开(公告)号：WO2007038164A3
公开(公告)日：2007-04-05
申请号：PCT/US2006/036738
申请日：2006-09-21
申请人： NANOSYS, INC. , PAN, Yaoling , CHEN, Jian , LEON, Francisco , MOSTARSHED, Shahriar , ROMANO, Linda T. , SAHI, Vijendra , STUMBO, David P.
发明人： PAN, Yaoling , CHEN, Jian , LEON, Francisco , MOSTARSHED, Shahriar , ROMANO, Linda T. , SAHI, Vijendra , STUMBO, David P.
IPC分类号： H01L29/06 , H01L21/225
摘要： Methods of doping nanostructures, such as nanowires, are disclosed. The methods provide a variety of approaches for improving existing methods of doping nanostructures. The embodiments include the use of a sacrificial layer to promote uniform dopant distribution within a nanostructure during post-nanostructure synthesis doping. In another embodiment, a high temperature environment is used to anneal nanostructure damage when high energy ion implantation is used. In another embodiment rapid thermal annealing is used to drive dopants from a dopant layer on a nanostructure into the nanostructure. In another embodiment a method for doping nanowires on a plastic substrate is provided that includes depositing a dielectric stack on a plastic substrate to protect the plastic substrate from damage during the doping process. An embodiment is also provided that includes selectively using high concentrations of dopant materials at various times in synthesizing nanostructures to realize novel crystallographic structures within the resulting nanostructure.

4. 发明申请

WO2006057818A2 CONTACT DOPING AND ANNEALING SYSTEMS AND PROCESSES FOR NANOWIRE THIN FILMS 审中-公开
标题翻译：联系DOPING和退火系统和纳米薄膜的工艺
公开(公告)号：WO2006057818A2
公开(公告)日：2006-06-01
申请号：PCT/US2005/040710
申请日：2005-11-10
申请人： NANOSYS, INC. , PAN, Yaoling , STUMBO, David, P.
发明人： PAN, Yaoling , STUMBO, David, P.
IPC分类号： H01L21/26
CPC分类号： H01L29/0665 , B82Y10/00 , B82Y40/00 , H01L29/0673 , H01L29/0676 , H01L29/068 , H01L29/66439 , H01L29/66469 , H01L29/66742 , H01L29/66772 , H01L29/7606 , H01L29/78696 , Y10S977/901 , Y10S977/963
摘要： Embodiments of the present invention are provided for improved contact doping and annealing systems and processes. In embodiments, a plasma ion immersion implantation (PIII) process is used for contact doping of nanowires and other nanoelement based thin film devices. According to further embodiments of the present invention, pulsed laser annealing using laser energy at relatively low laser fluences below about 100 mJ/cm 2 (e.g., less than about 50 mJ/cm 2 , e.g., between about 2 and 18 mJ/cm 2 ) is used to anneal nanowire and other nanoelement-based devices on substrates, such as low temperature flexible substrates, e.g., plastic substrates.
摘要翻译：提供本发明的实施例用于改进的接触掺杂和退火系统和工艺。在实施例中，等离子体离子浸没注入（PIII）工艺用于纳米线和其它基于纳米元件的薄膜器件的接触掺杂。根据本发明的另外的实施例，使用在低于约100mJ / cm 2（例如小于约50mJ / cm 2）的较低激光能量密度的激光能量进行脉冲激光退火， SUP>，例如约2和18mJ / cm 2之间）用于退火衬底上的纳米线和其它基于纳米元件的器件，例如低温柔性衬底，例如塑料衬底。

5. 发明申请

WO2005112122A2 NANOWIRE VARACTOR DIODE AND METHODS OF MAKING SAME 审中-公开
标题翻译：纳米级变压器二极管及其制造方法
公开(公告)号：WO2005112122A2
公开(公告)日：2005-11-24
申请号：PCT/US2005008891
申请日：2005-03-17
申请人： NANOSYS INC , STUMBO DAVID , CHEN JIAN , HEALD DAVID , PAN YAOLING
发明人： STUMBO DAVID , CHEN JIAN , HEALD DAVID , PAN YAOLING
IPC分类号： H01L29/06 , H01L29/93
CPC分类号： B82Y10/00 , H01L29/0665 , H01L29/0673 , H01L29/068 , H01L29/93 , Y10S977/762
摘要： A nanowire varactor diode and methods of making the same are disclosed. The structure comprises a coaxial capacitor running the length of the semiconductor nanowire. In one embodiment, a semiconductor nanowire of a first conductivity type is deposited on a substrate. An insulator is formed on at least a portion of the nanowire's surface. A region of the nanowire is doped with a second conductivity type material. A first electrical contact is formed on at least part of the insulator and the doped region. A second electrical contact is formed on a non-doped potion of the nanowire. During operation, the conductivity type at the surface of the nanowire inverts and a depletion region is formed upon application of a voltage to the first and second electrical contacts. The varactor diode thereby exhibits variable capacitance as a function of the applied voltage.
摘要翻译：公开了一种纳米线变容二极管及其制造方法。该结构包括运行半导体纳米线长度的同轴电容器。在一个实施例中，第一导电类型的半导体纳米线沉积在衬底上。在纳米线表面的至少一部分上形成绝缘体。纳米线的区域掺杂有第二导电类型的材料。在绝缘体和掺杂区域的至少一部分上形成第一电接触。在纳米线的非掺杂药液上形成第二电接触。在操作期间，纳米线表面的导电类型反转，并且在向第一和第二电触点施加电压时形成耗尽区。因此，变容二极管作为施加电压的函数呈现可变电容。

6. 发明申请

WO2013022643A1 AMORPHOUS OXIDE SEMICONDUCTOR THIN FILM TRANSISTOR FABRICATION METHOD 审中-公开
标题翻译：非晶氧化物半导体薄膜晶体管制造方法
公开(公告)号：WO2013022643A1
公开(公告)日：2013-02-14
申请号：PCT/US2012/048878
申请日：2012-07-30
申请人： QUALCOMM MEMS TECHNOLOGIES, INC. , PAN, Yaoling , KIM, Cheonhong , CHANG, Tallis Young
发明人： PAN, Yaoling , KIM, Cheonhong , CHANG, Tallis Young
IPC分类号： H01L29/66 , H01L29/786
CPC分类号： H01L29/78693 , H01L29/66969 , H01L29/78618 , H01L29/78696
摘要： This disclosure provides systems, methods and apparatus for fabricating thin film transistor devices. In one aspect, a substrate having a source area, a drain area, and a channel area is provided. The substrate also includes an oxide semiconductor layer, a first dielectric layer overlying the channel area of the substrate, and a first metal layer on the dielectric layer. Hydrogen ions are implanted with a plasma-immersion ion implantation process in the oxide semiconductor layer overlying the source area and the drain area of the substrate. The hydrogen ion implantation forms a doped n-type oxide semiconductor in the oxide semiconductor layer overlying the source area and the drain area of the substrate.
摘要翻译：本公开提供了用于制造薄膜晶体管器件的系统，方法和装置。一方面，提供了具有源极区域，漏极区域和沟道区域的衬底。衬底还包括氧化物半导体层，覆盖衬底的沟道区域的第一介电层和介电层上的第一金属层。在覆盖衬底的源极区域和漏极区域的氧化物半导体层中注入氢离子等离子体浸没离子注入工艺。氢离子注入在覆盖衬底的源极区和漏极区的氧化物半导体层中形成掺杂的n型氧化物半导体。

7. 发明申请

WO2007038164A2 METHODS FOR NANOSTRUCTURE DOPING 审中-公开
标题翻译：用于纳米结构的方法
公开(公告)号：WO2007038164A2
公开(公告)日：2007-04-05
申请号：PCT/US2006036738
申请日：2006-09-21
申请人： NANOSYS INC , PAN YAOLING , CHEN JIAN , LEON FRANCISCO , MOSTARSHED SHAHRIAR , ROMANO LINDA T , SAHI VIJENDRA , STUMBO DAVID P
发明人： PAN YAOLING , CHEN JIAN , LEON FRANCISCO , MOSTARSHED SHAHRIAR , ROMANO LINDA T , SAHI VIJENDRA , STUMBO DAVID P
IPC分类号： H01L29/06 , H01L21/225
CPC分类号： H01L29/0665 , B81C1/00698 , B81C2201/0173 , B82Y10/00 , H01L21/2256 , H01L21/268 , H01L29/0673
摘要： Methods of doping nanostructures, such as nanowires, are disclosed. The methods provide a variety of approaches for improving existing methods of doping nanostructures. The embodiments include the use of a sacrificial layer to promote uniform dopant distribution within a nanostructure during post-nanostructure synthesis doping. In another embodiment, a high temperature environment is used to anneal nanostructure damage when high energy ion implantation is used. In another embodiment rapid thermal annealing is used to drive dopants from a dopant layer on a nanostructure into the nanostructure. In another embodiment a method for doping nanowires on a plastic substrate is provided that includes depositing a dielectric stack on a plastic substrate to protect the plastic substrate from damage during the doping process. An embodiment is also provided that includes selectively using high concentrations of dopant materials at various times in synthesizing nanostructures to realize novel crystallographic structures within the resulting nanostructure.
摘要翻译：公开了掺杂纳米结构的方法，例如纳米线。该方法提供了改进现有的纳米结构掺杂方法的各种方法。实施例包括在后纳米结构合成掺杂期间使用牺牲层来促进纳米结构内的均匀掺杂剂分布。在另一个实施例中，当使用高能离子注入时，使用高温环境退火纳米结构损伤。在另一个实施方案中，使用快速热退火来将掺杂剂从纳米结构上的掺杂剂层驱动到纳米结构中。在另一个实施例中，提供了一种在塑料衬底上掺杂纳米线的方法，其包括在塑料衬底上沉积电介质叠层以保护塑料衬底免于在掺杂过程期间损坏。还提供了一种实施方案，其包括在合成纳米结构中在不同时间选择性地使用高浓度的掺杂剂材料，以在所得纳米结构内实现新的晶体结构。

8. 发明申请

WO2007030126A2 METHOD, SYSTEM, AND APPARATUS FOR GATING CONFIGURATIONS AND IMPROVED CONTACTS IN NANOWIRE-BASED ELECTRONIC DEVICES 审中-公开
标题翻译：用于在纳米级电子设备中进行配置和改进联系的方法，系统和设备
公开(公告)号：WO2007030126A2
公开(公告)日：2007-03-15
申请号：PCT/US2005/037237
申请日：2005-10-14
申请人： NANOSYS, INC. , MOSTARSHED, Shahriar , CHEN, Jian , LEON, Francisco , PAN, Yaoling , ROMANO, Linda T.
发明人： MOSTARSHED, Shahriar , CHEN, Jian , LEON, Francisco , PAN, Yaoling , ROMANO, Linda T.
IPC分类号： H01L29/76
CPC分类号： H01L29/0665 , B82Y10/00 , H01L29/0673 , H01L29/42384 , H01L29/42392 , H01L29/775 , H01L29/785 , H01L29/78645 , H01L29/78681 , H01L29/7869 , Y10S977/762 , Y10S977/932 , Y10S977/938
摘要： Methods, systems, and apparatuses for electronic devices having improved gate structures are described. An electronic device includes at least one nanowire. A gate contact is positioned along at least a portion of a length of the at least one nanowire. A dielectric material layer is between the gate contact and the at least one nanowire. A source contact and a drain contact are in contact with the at least one nanowire. At least a portion of the source contact and/or the drain contact overlaps with the gate contact along the nanowire the length. In another aspect, an electronic device includes a nanowire having a semiconductor core surrounded by an insulating shell layer. A ring shaped first gate region surrounds the nanowire along a portion of the length of the nanowire. A second gate region is positioned along the length of the nanowire between the nanowire and the substrate. A source contact and a drain contact are coupled to the semiconductor core of the nanowire at respective exposed portions of the semiconductor core.
摘要翻译：描述了具有改进的门结构的电子设备的方法，系统和装置。电子装置包括至少一个纳米线。栅极接触沿至少一个纳米线的长度的至少一部分定位。介电材料层在栅极接触和至少一个纳米线之间。源极触点和漏极触点与至少一个纳米线接触。源极触点和/或漏极触点的至少一部分沿着该纳米线的长度与栅极触点重叠。另一方面，一种电子器件包括具有被绝缘壳层包围的半导体芯的纳米线。环形第一栅极区域沿着纳米线长度的一部分包围纳米线。第二栅极区沿着纳米线和衬底之间的纳米线的长度定位。源极触点和漏极触点在半导体芯的相应的暴露部分处耦合到纳米线的半导体芯。

9. 发明申请

WO2006078281A3 SYSTEMS AND METHODS FOR HARVESTING AND INTEGRATING NANOWIRES 审中-公开
公开(公告)号：WO2006078281A3
公开(公告)日：2006-07-27
申请号：PCT/US2005/014922
申请日：2005-04-29
申请人： NANOSYS, INC. , ROMANO, Linda, T. , CHEN, Jian , DUAN, Xiangfeng , DUBROW, Robert, S. , EMPEDOCLES, Stephen, A. , GOLDMAN, Jay, L. , HAMILTON, James, M. , HEALD, David, L. , LEMMI, Francesco , NIU, Chunming , PAN, Yaoling , PONTIS, George , SAHI, Vijendra , SCHER, Erik, C. , STUMBO, David, P. , WHITEFORD, Jeffery, A.
发明人： ROMANO, Linda, T. , CHEN, Jian , DUAN, Xiangfeng , DUBROW, Robert, S. , EMPEDOCLES, Stephen, A. , GOLDMAN, Jay, L. , HAMILTON, James, M. , HEALD, David, L. , LEMMI, Francesco , NIU, Chunming , PAN, Yaoling , PONTIS, George , SAHI, Vijendra , SCHER, Erik, C. , STUMBO, David, P. , WHITEFORD, Jeffery, A.
IPC分类号： H01L21/20 , H01L29/06 , H01L21/335
摘要： The present invention is directed to methods to harvest, integrate and exploit nanomaterials, and particularly elongated nanowire materials. The invention provides methods for harvesting nanowires that include selectively etching a sacrificial layer placed on a nanowire growth substrate to remove nanowires. The invention also provides methods for integrating nanowires into electronic devices that include placing an outer surface of a cylinder in contact with a fluid suspension of nanowires and rolling the nanowire coated cylinder to deposit nanowires onto a surface. Methods are also provided to deposit nanowires using an ink-jet printer or an aperture to align nanowires. Additional aspects of the invention provide methods for preventing gate shorts in nanowire based transistors. Additional methods for harvesting and integrating nanowires are provided.

10. 发明申请

WO2007136412A2 METHODS FOR ORIENTED GROWTH OF NANOWIRES ON PATTERNED SUBSTRATES 审中-公开
标题翻译：用于在图案化基底上的纳米线的生长的方法
公开(公告)号：WO2007136412A2
公开(公告)日：2007-11-29
申请号：PCT/US2006/048456
申请日：2006-12-20
申请人： NANOSYS, INC. , PAN, Yaoling , DUAN, Xiangfeng , DUBROW, Robert, S. , GOLDMAN, Jay, L. , MOSTARSHED, Shahriar , NIU, Chunming , ROMANO, Linda, T. , STUMBO, David, P. , FISCHER-COLBRIE, Alice , SAHI, Vijendra , ROBBINS, Virginia
发明人： PAN, Yaoling , DUAN, Xiangfeng , DUBROW, Robert, S. , GOLDMAN, Jay, L. , MOSTARSHED, Shahriar , NIU, Chunming , ROMANO, Linda, T. , STUMBO, David, P. , FISCHER-COLBRIE, Alice , SAHI, Vijendra , ROBBINS, Virginia
IPC分类号： B21C1/00
CPC分类号： C30B29/605 , B82Y30/00 , C30B11/12 , C30B29/06 , Y10T428/24917
摘要： The present invention is directed to systems and methods for nanowire growth and harvesting. In an embodiment, methods for nanowire growth and doping are provided, including methods for epitaxial oriented nanowire growth using a combination of silicon precursors, as well as us of patterned substrates to grow oriented nanowires. In a further aspect of the invention, methods to improve nanowire quality through the use of sacrifical growth layers are provided. In another aspect of the invention, methods for transferring nanowires from one substrate to another substrate are provided.
摘要翻译：本发明涉及用于纳米线生长和收获的系统和方法。在一个实施例中，提供了用于纳米线生长和掺杂的方法，包括使用硅前体的组合的外延取向纳米线生长的方法，以及我们用于生长取向的纳米线的图案化衬底。在本发明的另一方面，提供了通过使用牺牲生长层来提高纳米线质量的方法。在本发明的另一方面，提供了将纳米线从一个衬底转移到另一个衬底的方法。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式