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1. 发明申请

US20110283051A1 MOVING EXECUTABLE CODE FROM A FIRST REGION OF A NON-VOLATILE MEMORY TO A SECOND REGION OF THE NON-VOLATILE MEMORY 有权
标题翻译：将非易失性存储器的第一个区域的可执行代码移动到非易失性存储器的第二个区域
公开(公告)号：US20110283051A1
公开(公告)日：2011-11-17
申请号：US12780149
申请日：2010-05-14
申请人： OPHER LIEBER , MENAHEM LASSER
发明人： OPHER LIEBER , MENAHEM LASSER
IPC分类号： G06F12/16
CPC分类号： G06F11/1417
摘要： A data storage device includes a controller and a non-volatile memory coupled to the controller. The non-volatile memory includes executable boot code that is executable by a processor associated with the data storage device. The controller is configured to read a first portion of the executable boot code from a first region of the non-volatile memory, and in response to detecting a condition, move a second portion of the executable boot code in a second region of the non-volatile memory to a third region of the non-volatile memory.
摘要翻译：数据存储设备包括耦合到控制器的控制器和非易失性存储器。非易失性存储器包括可由与数据存储设备相关联的处理器执行的可执行引导代码。所述控制器被配置为从所述非易失性存储器的第一区域读取所述可执行引导代码的第一部分，并且响应于检测到条件，在所述非易失性存储器的第二区域中移动所述可执行引导代码的第二部分，易失性存储器到非易失性存储器的第三区域。

2. 发明授权

US08407399B2 Method and apparatus for enforcing a flash memory caching policy 有权
标题翻译：执行闪存缓存策略的方法和装置
公开(公告)号：US08407399B2
公开(公告)日：2013-03-26
申请号：US12260135
申请日：2008-10-29
申请人： Menahem Lasser , Itshak Afriat , Opher Lieber
发明人： Menahem Lasser , Itshak Afriat , Opher Lieber
IPC分类号： G06F12/08
CPC分类号： G06F12/0246 , G06F12/0888 , G06F2212/7208
摘要： Methods, apparatus and computer medium for enforcing one or more cache management policies are disclosed herein. In some embodiments, a flash memory of a storage device includes a plurality of flash memory dies each flash memory die including a respective cache storage area and a respective main storage area. A determination is made, for data that is received from an external host device to which main storage area the received data is addressed thereby specifying one of the plurality of flash memory dies as a target die for the received data. Whenever the received data is written into a cache storage area before being written into a main storage area, the received data is written into the cache storage area of the specified target die.
摘要翻译：本文公开了用于执行一个或多个缓存管理策略的方法，装置和计算机介质。在一些实施例中，存储设备的闪速存储器包括多个闪速存储器管芯，每个闪速存储器管芯包括相应的缓存存储区域和相应的主存储区域。对于从接收到的数据被存储到主存储区域的外部主机设备接收的数据进行确定，从而将多个闪速存储器管芯之一指定为接收数据的目标管芯。无论何时在被写入主存储区域之前将接收的数据写入高速缓存存储区域中，将接收的数据写入指定目标管芯的高速缓存存储区域中。

3. 发明申请

US20100106890A1 METHOD AND APPARATUS FOR ENFORCING A FLASH MEMORY CACHING POLICY 有权
标题翻译：用于执行闪存存储器缓存策略的方法和装置
公开(公告)号：US20100106890A1
公开(公告)日：2010-04-29
申请号：US12260135
申请日：2008-10-29
申请人： Menahem LASSER , Izhak Afriat , Opher Lieber
发明人： Menahem LASSER , Izhak Afriat , Opher Lieber
IPC分类号： G06F12/00
CPC分类号： G06F12/0246 , G06F12/0888 , G06F2212/7208
摘要： Methods, apparatus and computer medium for enforcing one or more cache management policies are disclosed herein. In some embodiments, a flash memory of a storage device includes a plurality of flash memory dies each flash memory die including a respective cache storage area and a respective main storage area. A determination is made, for data that is received from an external host device to which main storage area the received data is addressed thereby specifying one of the plurality of flash memory dies as a target die for the received data. Whenever the received data is written into a cache storage area before being written into a main storage area, the received data is written into the cache storage area of the specified target die.
摘要翻译：本文公开了用于执行一个或多个缓存管理策略的方法，装置和计算机介质。在一些实施例中，存储设备的闪速存储器包括多个闪速存储器管芯，每个闪速存储器管芯包括相应的缓存存储区域和相应的主存储区域。对于从接收到的数据被存储到主存储区域的外部主机设备接收的数据进行确定，从而将多个闪速存储器管芯之一指定为接收数据的目标管芯。无论何时在被写入主存储区域之前将接收的数据写入高速缓存存储区域中，将接收的数据写入指定目标管芯的高速缓存存储区域中。

4. 发明申请

US20140281122A1 MULTI-LEVEL TABLE DELTAS 有权
标题翻译：多层次表
公开(公告)号：US20140281122A1
公开(公告)日：2014-09-18
申请号：US13803645
申请日：2013-03-14
申请人： Opher Lieber
发明人： Opher Lieber
IPC分类号： G06F12/02
CPC分类号： G06F12/0246 , G06F12/0804 , G06F12/0893 , G06F2212/7203 , G06F2212/7207
摘要： A memory system or flash card may include an algorithm or process for managing the handling of large tables in memory. A delta may be used for each table to accumulate updates. There may be a plurality of deltas for a multi-level delta structure. In one example, the first level delta is stored in random access memory (RAM), while the other level deltas are stored in the flash memory. Multiple-level deltas may improve the number of flash writes and reduce the number and amount of each flush to the actual table in flash. The use of multi-level deltas may improve performance by more efficiently writing to the table in flash.
摘要翻译：存储器系统或闪存卡可以包括用于管理存储器中的大表的处理的算法或过程。每个表可以使用增量来累积更新。多级三角结构可能有多个三角形。在一个示例中，第一级增量存储在随机存取存储器（RAM）中，而其他级别的三角形存储在闪速存储器中。多级增量可以提高闪存写入次数，并减少闪存中实际表中每次刷新的次数和数量。使用多级三角形可以通过更有效地写入闪存中的表来提高性能。

5. 发明授权

US08452937B2 Moving executable code from a first region of a non-volatile memory to a second region of the non-volatile memory to reduce read disturb 有权
标题翻译：将可执行代码从非易失性存储器的第一区域移动到非易失性存储器的第二区域以减少读取干扰
公开(公告)号：US08452937B2
公开(公告)日：2013-05-28
申请号：US12780149
申请日：2010-05-14
申请人： Opher Lieber , Menahem Lasser
发明人： Opher Lieber , Menahem Lasser
IPC分类号： G06F12/16
CPC分类号： G06F11/1417
摘要： A data storage device includes a controller and a non-volatile memory coupled to the controller. The non-volatile memory includes executable boot code that is executable by a processor associated with the data storage device. The controller is configured to read a first portion of the executable boot code from a first region of the non-volatile memory, and in response to detecting a condition, move a second portion of the executable boot code in a second region of the non-volatile memory to a third region of the non-volatile memory.
摘要翻译：数据存储设备包括耦合到控制器的控制器和非易失性存储器。非易失性存储器包括可由与数据存储设备相关联的处理器执行的可执行引导代码。所述控制器被配置为从所述非易失性存储器的第一区域读取所述可执行引导代码的第一部分，并且响应于检测到条件，在所述非易失性存储器的第二区域中移动所述可执行引导代码的第二部分，易失性存储器到非易失性存储器的第三区域。

6. 发明授权

US08301979B2 Low density parity code (LDPC) decoding for memory with multiple log likelihood ratio (LLR) decoders 有权
标题翻译：具有多对数似然比（LLR）解码器的存储器的低密度奇偶校验码（LDPC）解码
公开(公告)号：US08301979B2
公开(公告)日：2012-10-30
申请号：US12574982
申请日：2009-10-07
申请人： Eran Sharon , Idan Alrod , Ariel Navon , Opher Lieber
发明人： Eran Sharon , Idan Alrod , Ariel Navon , Opher Lieber
IPC分类号： G11C29/00
CPC分类号： H03M13/6591 , G06F11/1072 , H03M13/1108 , H03M13/1128 , H03M13/1142 , H03M13/45
摘要： Data stored in memory is decoded using iterative probabilistic decoding and multiple decoders. A first decoder attempts to decode a representation of a codeword. If the attempt is unsuccessful, a second decoder attempts to decode the representation of a codeword. The second decoder may have a lower resolution than the first decoder. Probability values such as logarithmic likelihood ratio (LLR) values may be clipped in the second decoder. This approach can overcome trapping sets while exhibiting low complexity and high performance. Further, it can be implemented on existing decoders such as those used in current memory devices.
摘要翻译：使用迭代概率解码和多个解码器对存储在存储器中的数据进行解码。第一解码器尝试对码字的表示进行解码。如果尝试不成功，则第二解码器尝试对码字的表示进行解码。第二解码器可以具有比第一解码器更低的分辨率。诸如对数似然比（LLR）值之类的概率值可以在第二解码器中被裁剪。这种方法可以克服陷阱集，同时表现出低复杂性和高性能。此外，它可以在诸如当前存储器件中使用的解码器之类的现有解码器上实现。

7. 发明申请

US20090276562A1 Flash cache flushing method and system 有权
标题翻译： Flash缓存刷新方法和系统
公开(公告)号：US20090276562A1
公开(公告)日：2009-11-05
申请号：US12214291
申请日：2008-05-01
申请人： Opher Lieber
发明人： Opher Lieber
IPC分类号： G06F12/02
CPC分类号： G06F12/0804 , G06F12/0246
摘要： A flash memory system that uses repeated writing of the data to achieve stable storage, is adapted for efficient cache flushing operations by utilizing a part of the non-volatile flash memory array as a designated buffer for the data, in which data integrity is retained until all repeat writing thereof is complete. Repeated writing is carried out from the designated buffer directly to the final storage locations in the flash memory array, for example using simple internal copy back operations.
摘要翻译：使用数据的重复写入来实现稳定存储的闪存系统适用于通过利用非易失性闪存阵列的一部分作为用于数据的指定缓冲器来进行有效的高速缓存冲刷操作，其中保留数据完整性直到所有重复写作都完成了。重写的写入从指定的缓冲区直接执行到闪存阵列中的最终存储位置，例如使用简单的内部复制操作。

8. 发明申请

US20090172286A1 Method And System For Balancing Host Write Operations And Cache Flushing 有权
标题翻译：平衡主机写入操作和缓存刷新的方法和系统
公开(公告)号：US20090172286A1
公开(公告)日：2009-07-02
申请号：US11967369
申请日：2007-12-31
申请人： Menahem Lasser , Itshak Afriat , Opher Lieber , Mark Shlick
发明人： Menahem Lasser , Itshak Afriat , Opher Lieber , Mark Shlick
IPC分类号： G06F12/00
CPC分类号： G06F12/0893 , G06F12/0246 , G06F12/0804 , G06F12/0866 , G06F2212/1024 , G06F2212/313 , G06F2212/7203 , G06F2212/7208
摘要： A method and system for balancing host write operations and cache flushing is disclosed. The method may include steps of determining an available capacity in a cache storage portion of a self-caching storage device, determining a ratio of cache flushing steps to host write commands if the available capacity is below a desired threshold and interleaving cache flushing steps with host write commands to achieve the ratio. The cache flushing steps may be executed by maintaining a storage device busy status after executing a host write command and utilizing this additional time to copy a portion of the data from the cache storage into the main storage. The system may include a cache storage, a main storage and a controller configured to determine and execute a ratio of cache flushing steps to host write commands by executing cache flushing steps while maintaining a busy status after a host write command.
摘要翻译：公开了一种用于平衡主机写入操作和缓存冲洗的方法和系统。该方法可以包括以下步骤：确定自缓存存储设备的高速缓存存储部分中的可用容量，如果可用容量低于期望阈值，则确定高速缓存刷新步骤与主机写入命令的比率，并且与主机交织高速缓存刷新步骤写命令来实现比例。可以通过在执行主机写入命令之后维持存储设备忙状态并利用该附加时间将数据的一部分从高速缓存存储器复制到主存储器中来执行高速缓冲存储器刷新步骤。该系统可以包括高速缓存存储器，主存储器和控制器，该控制器被配置为通过在主机写入命令之后保持忙状态的同时执行高速缓冲存储器刷新步骤来确定和执行高速缓存刷新步骤以主机写入命令的比率。

9. 发明授权

US09727453B2 Multi-level table deltas 有权
公开(公告)号：US09727453B2
公开(公告)日：2017-08-08
申请号：US13803645
申请日：2013-03-14
申请人： Opher Lieber
发明人： Opher Lieber
IPC分类号： G06F12/02 , G06F12/0804 , G06F12/0893
CPC分类号： G06F12/0246 , G06F12/0804 , G06F12/0893 , G06F2212/7203 , G06F2212/7207
摘要： A memory system or flash card may include an algorithm or process for managing the handling of large tables in memory. A delta may be used for each table to accumulate updates. There may be a plurality of deltas for a multi-level delta structure. In one example, the first level delta is stored in random access memory (RAM), while the other level deltas are stored in the flash memory. Multiple-level deltas may improve the number of flash writes and reduce the number and amount of each flush to the actual table in flash. The use of multi-level deltas may improve performance by more efficiently writing to the table in flash.

10. 发明授权

US09594679B2 Flash cache flushing method and system 有权
标题翻译： Flash缓存刷新方法和系统
公开(公告)号：US09594679B2
公开(公告)日：2017-03-14
申请号：US12214291
申请日：2008-05-01
申请人： Opher Lieber
发明人： Opher Lieber
IPC分类号： G06F12/02 , G06F12/08
CPC分类号： G06F12/0804 , G06F12/0246
摘要： A flash memory system that uses repeated writing of the data to achieve stable storage, is adapted for efficient cache flushing operations by utilizing a part of the non-volatile flash memory array as a designated buffer for the data, in which data integrity is retained until all repeat writing thereof is complete. Repeated writing is carried out from the designated buffer directly to the final storage locations in the flash memory array, for example using simple internal copy back operations.
摘要翻译：使用数据的重复写入来实现稳定存储的闪存系统适用于通过利用非易失性闪存阵列的一部分作为用于数据的指定缓冲器来进行有效的高速缓存冲刷操作，其中保留数据完整性直到所有重复写作都完成了。重写的写入从指定的缓冲区直接执行到闪存阵列中的最终存储位置，例如使用简单的内部复制操作。

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