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1. 发明申请

WO1998019242A1 DATA PROCESSOR AND DATA PROCESSING SYSTEM 审中-公开
标题翻译：数据处理器和数据处理系统
公开(公告)号：WO1998019242A1
公开(公告)日：1998-05-07
申请号：PCT/JP1996003172
申请日：1996-10-30
申请人： HITACHI, LTD. , HITACHI ULSI ENGINEERING CORP. , YAMAZAKI, Takanaga , AKAO, Yasushi , KURAKAZU, Keiichi , OHIZUMI, Masayasu , KATAOKA, Takeshi , NAKAI, Tatsuo , MIYAZAKI, Mitsuhiro , MURAYAMA, Yosuke
发明人： HITACHI, LTD. , HITACHI ULSI ENGINEERING CORP.
IPC分类号： G06F12/08
CPC分类号： G06F12/0864
摘要： A data processor including a central processing unit, a plurality of direct map cache memories (3, 4), and a plurality of area designation circuits (5, 6) for designating variably the positions and the sizes of address areas in a memory space managed by the central processing unit, wherein the address areas designated by a plurality of area designation circuits are partially overlapped, so that the overlapped area (Eco) functions as two-way set associative cache memories by combining a plurality of cache memories. Each cache memory functions as a direct map cache memory for the non-overlap area. Information is predetermined about locations of routines in the address area and the required speed for desirable data processing. When a cache object area is assigned to a plurality of cache memories, they are operated as a set associative cache for a task or a data area particularly requiring a higher operation speed. In this way, the cache hit rate in a necessary area can be improved and the system can be optimized.
摘要翻译：一种数据处理器，包括中央处理单元，多个直接地图高速缓冲存储器（3,4）和多个区域指定电路（5,6），用于可变地指定管理的存储器空间中的地址区域的位置和大小通过中央处理单元，其中由多个区域指定电路指定的地址区域部分重叠，从而通过组合多个高速缓冲存储器，重叠区域（Eco）用作双向组关联高速缓存存储器。每个缓存存储器用作非重叠区域的直接映射缓存存储器。关于地址区域中的例程的位置和期望的数据处理所需的速度预先确定信息。当将高速缓存对象区域分配给多个高速缓存存储器时，它们被操作为特定需要较高操作速度的任务或数据区域的组合关联高速缓存。以这种方式，可以提高必要区域中的高速缓存命中率，并且可以优化系统。

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