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1. 发明申请

WO2019125497A1 INTERCONNECT STRUCTURES FOR INTEGRATED CIRCUITS 审中-公开
公开(公告)号：WO2019125497A1
公开(公告)日：2019-06-27
申请号：PCT/US2017/068359
申请日：2017-12-22
申请人： INTEL CORPORATION , LAJOIE, Travis , GHANI, Tahir , KAVALIEROS, Jack T. , OGADHOH, Shem O. , WANG, Yih , SELL, Bernhard , GARDINER, Allen , LIN, Blake , ALZATE VINASCO, Juan G. , WANG, Pei-Hua , KU, Chieh-Jen , SHARMA, Abhishek A.
发明人： LAJOIE, Travis , GHANI, Tahir , KAVALIEROS, Jack T. , OGADHOH, Shem O. , WANG, Yih , SELL, Bernhard , GARDINER, Allen , LIN, Blake , ALZATE VINASCO, Juan G. , WANG, Pei-Hua , KU, Chieh-Jen , SHARMA, Abhishek A.
IPC分类号： H01L21/768
摘要： Embodiments herein describe techniques for a semiconductor device having an interconnect structure above a substrate. The interconnect structure may include an inter-level dielectric (ILD) layer and a separation layer above the ILD layer. A first conductor and a second conductor may be within the ILD layer. The first conductor may have a first physical configuration, and the second conductor may have a second physical configuration different from the first physical configuration. Other embodiments may be described and/or claimed.

2. 发明申请

WO2013101202A1 TECHNIQUES FOR PHASE TUNING FOR PROCESS OPTIMIZATION 审中-公开
标题翻译：用于过程优化的相位调整技术
公开(公告)号：WO2013101202A1
公开(公告)日：2013-07-04
申请号：PCT/US2011/068157
申请日：2011-12-30
申请人： INTEL CORPORATION , NYHUS, Paul A. , OGADHOH, Shem O. , SIVAKUMAR, Swaminathan , JEONG, Seongtae
发明人： NYHUS, Paul A. , OGADHOH, Shem O. , SIVAKUMAR, Swaminathan , JEONG, Seongtae
IPC分类号： H01L21/027 , G03F1/36
CPC分类号： G06F17/5009 , G03F1/36 , G03F1/70 , G06F17/5068
摘要： Techniques are provided for determining how thick or how deep to make the phased regions of a lithography mask. One example embodiment provides a method that includes: providing first mask layout design including a first test set, and providing a second mask layout design including a second test set, wherein the second test set is larger than the first test set; simulating critical dimensions through focus of structures of interest in the first test set for a range of phase depths/thicknesses, and selecting an initial preferred mask phase depth/thickness based on results of the simulating; and generating a fast thick-mask model (FTM) at the initial preferred phase depth/thickness, and correcting the second test set of the second mask layout design using the FTM, thereby providing an optimized mask layout design. A mask having the optimized mask layout design may be implemented to give the optimum patterning.
摘要翻译：提供了用于确定制造光刻掩模的相位区域的厚度或深度的技术。一个示例性实施例提供了一种方法，其包括：提供包括第一测试集的第一掩模布局设计，以及提供包括第二测试集的第二掩模布局设计，其中所述第二测试集大于所述第一测试集; 通过针对一系列相位深度/厚度的第一测试集合中关注的结构的焦点来模拟关键尺寸，并且基于模拟结果选择初始优选的掩模相位深度/厚度; 并且以最初的优选相位深度/厚度生成快速厚掩模模型（FTM），并且使用FTM校正第二掩模布局设计的第二测试集，由此提供优化的掩模布局设计。可以实施具有优化的掩模布局设计的掩模以给出最佳图案化。

3. 发明申请

WO2013101103A1 LITHOGRAPHY MASK HAVING SUB-RESOLUTION PHASED ASSIST FEATURES 审中-公开
标题翻译：具有分解相位辅助功能的LITHOGRAPHY MASK
公开(公告)号：WO2013101103A1
公开(公告)日：2013-07-04
申请号：PCT/US2011/067924
申请日：2011-12-29
申请人： INTEL CORPORATION , OGADHOH, Shem O. , WALLACE, Charles H. , PEARMAN, Ryan , HENRICHS, Sven , SUNDARAMURTHY, Arvind , SIVAKUMAR, Swaminathan
发明人： OGADHOH, Shem O. , WALLACE, Charles H. , PEARMAN, Ryan , HENRICHS, Sven , SUNDARAMURTHY, Arvind , SIVAKUMAR, Swaminathan
IPC分类号： G03F1/38 , G03F1/40 , G03F1/50
CPC分类号： G03F1/38
摘要： Techniques are disclosed for using sub-resolution phased assist features (SPAF) in a lithography mask to improve through process pattern fidelity and/or mitigate inverted aerial image problems. The technique also may be used to improve image contrast in non-inverted weak image sites. The use of SPAF in accordance with some such embodiments requires no adjustment to existing design rules, although adjustments can be made to enable compliance with mask inspection constraints. The use of SPAF also does not require changing existing fab or manufacturing processes, especially if such processes already comprehend phased shift mask capabilities. The SPAFs can be used to enhance aerial image contrast, without the SPAFs themselves printing. In addition, the SPAF phase etch depth can be optimized so as to make adjustments to a given predicted printed feature critical dimension.
摘要翻译：公开了在光刻掩模中使用子分辨率相控辅助特征（SPAF）来改进过程模式保真度和/或减轻倒置的空中图像问题的技术。该技术也可用于改善非反转弱图像位置中的图像对比度。根据一些这样的实施例的SPAF的使用不需要调整现有的设计规则，尽管可以进行调整以使得能够符合掩模检查约束。使用SPAF也不需要改变现有的晶圆厂或制造工艺，特别是如果这些工艺已经理解了相位移位掩模功能。 SPAF可以用于增强空中图像对比度，而不需要SPAF自身的打印。此外，可以优化SPAF相蚀刻深度，以便对给定的预测印刷特征临界尺寸进行调整。

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