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1. 发明申请

US20110273939A1 NONVOLATILE MEMORY DEVICE 审中-公开
标题翻译：非易失性存储器件
公开(公告)号：US20110273939A1
公开(公告)日：2011-11-10
申请号：US13187035
申请日：2011-07-20
申请人： Tetsuya MURAKAMI , Nobuyoshi Nara , Kenichi Imamiya
发明人： Tetsuya MURAKAMI , Nobuyoshi Nara , Kenichi Imamiya
IPC分类号： G11C5/14
CPC分类号： G11C5/143
摘要： A nonvolatile memory device includes a nonvolatile memory and a controller unit for the nonvolatile memory. The nonvolatile memory and the controller unit include a first logic section and a second logic section, respectively. The nonvolatile memory includes a voltage detector configured to detect a power supply voltage externally supplied to the nonvolatile memory and the controller unit, and an output of the detection is supplied to the first logic section of the nonvolatile memory provided with the voltage detector, and also to the second logic section of the controller unit and/or a logic section of at least one added nonvolatile memory via a buffer amplifier, simultaneously.
摘要翻译：非易失性存储器件包括非易失性存储器和用于非易失性存储器的控制器单元。非易失性存储器和控制器单元分别包括第一逻辑部分和第二逻辑部分。非易失性存储器包括：电压检测器，被配置为检测外部提供给非易失性存储器和控制器单元的电源电压，并且将检测的输出提供给设置有电压检测器的非易失性存储器的第一逻辑部分，并且还同时通过缓冲放大器将控制器单元的第二逻辑部分和/或至少一个相加的非易失性存储器的逻辑部分。

2. 发明申请

US20090008461A1 SEMICONDUCTOR DEVICE AND MEMORY CARD HAVING THE SAME 有权
标题翻译：半导体器件和存储卡
公开(公告)号：US20090008461A1
公开(公告)日：2009-01-08
申请号：US12115418
申请日：2008-05-05
申请人： Nobuyoshi NARA
发明人： Nobuyoshi NARA
IPC分类号： G06K19/06
CPC分类号： G06K19/07
摘要： A semiconductor device includes a first circuit which operates in accordance with an internal clock, a second circuit which generates information of which an external apparatus is to be notified, an interface section which notifies the external apparatus of the information generated by the second circuit without using the first circuit upon receiving a predetermined command from the external apparatus, and a plurality of terminals each of which is connectable to one of power terminals and ground terminals provided on a substrate. The information is determined depending on whether each of the plurality of terminals is electrically connected to the power terminal or ground terminal on the substrate.
摘要翻译：半导体器件包括：根据内部时钟进行工作的第一电路，产生要通知外部设备的信息的第二电路;接口部，其向外部设备通知由第二电路生成的信息，而不使用所述第一电路在从外部设备接收到预定命令时，以及多个端子，每个端子可连接到设置在基板上的电源端子和接地端子之一。信息取决于多个端子中的每一个是否电连接到基板上的电源端子或接地端子。

3. 发明申请

US20090154280A1 NONVOLATILE MEMORY DEVICE 有权
标题翻译：非易失性存储器件
公开(公告)号：US20090154280A1
公开(公告)日：2009-06-18
申请号：US12332487
申请日：2008-12-11
申请人： Tetsuya MURAKAMI , Nobuyoshi Nara , Kenichi Imamiya
发明人： Tetsuya MURAKAMI , Nobuyoshi Nara , Kenichi Imamiya
IPC分类号： G11C5/14
CPC分类号： G11C5/143
摘要： A nonvolatile memory device includes a nonvolatile memory and a controller unit for the nonvolatile memory. The nonvolatile memory and the controller unit include a first logic section and a second logic section, respectively. The nonvolatile memory includes a voltage detector configured to detect a power supply voltage externally supplied to the nonvolatile memory and the controller unit, and an output of the detection is supplied to the first logic section of the nonvolatile memory provided with the voltage detector, and also to the second logic section of the controller unit and/or a logic section of at least one added nonvolatile memory via a buffer amplifier, simultaneously.
摘要翻译：非易失性存储器件包括非易失性存储器和用于非易失性存储器的控制器单元。非易失性存储器和控制器单元分别包括第一逻辑部分和第二逻辑部分。非易失性存储器包括：电压检测器，被配置为检测外部提供给非易失性存储器和控制器单元的电源电压，并且将检测的输出提供给设置有电压检测器的非易失性存储器的第一逻辑部分，并且还同时通过缓冲放大器将控制器单元的第二逻辑部分和/或至少一个相加的非易失性存储器的逻辑部分。

4. 发明申请

US20060289660A1 Semiconductor device and memory card having the same 有权
标题翻译：半导体装置和存储卡具有相同的功能
公开(公告)号：US20060289660A1
公开(公告)日：2006-12-28
申请号：US11513025
申请日：2006-08-31
申请人： Nobuyoshi Nara
发明人： Nobuyoshi Nara
IPC分类号： G06K19/06
CPC分类号： G06K19/07
摘要： A semiconductor device includes a first circuit which operates in accordance with an internal clock, a second circuit which generates information of which an external apparatus is to be notified, an interface section which notifies the external apparatus of the information generated by the second circuit without using the first circuit upon receiving a predetermined command from the external apparatus, and a plurality of terminals each of which is connectable to one of power terminals and ground terminals provided on a substrate. The information is determined depending on whether each of the plurality of terminals is electrically connected to the power terminal or ground terminal on the substrate.
摘要翻译：半导体器件包括：根据内部时钟进行工作的第一电路，产生要通知外部设备的信息的第二电路;接口部，其向外部设备通知由第二电路生成的信息，而不使用所述第一电路在从外部设备接收到预定命令时，以及多个端子，每个端子可连接到设置在基板上的电源端子和接地端子之一。信息取决于多个端子中的每一个是否电连接到基板上的电源端子或接地端子。

5. 发明授权

US08023355B2 Nonvolatile memory device 有权
标题翻译：非易失性存储器件
公开(公告)号：US08023355B2
公开(公告)日：2011-09-20
申请号：US12332487
申请日：2008-12-11
申请人： Tetsuya Murakami , Nobuyoshi Nara , Kenichi Imamiya
发明人： Tetsuya Murakami , Nobuyoshi Nara , Kenichi Imamiya
IPC分类号： G11C5/14
CPC分类号： G11C5/143
摘要： A nonvolatile memory device includes a nonvolatile memory and a controller unit for the nonvolatile memory. The nonvolatile memory and the controller unit include a first logic section and a second logic section, respectively. The nonvolatile memory includes a voltage detector configured to detect a power supply voltage externally supplied to the nonvolatile memory and the controller unit, and an output of the detection is supplied to the first logic section of the nonvolatile memory provided with the voltage detector, and also to the second logic section of the controller unit and/or a logic section of at least one added nonvolatile memory via a buffer amplifier, simultaneously.
摘要翻译：非易失性存储器件包括非易失性存储器和用于非易失性存储器的控制器单元。非易失性存储器和控制器单元分别包括第一逻辑部分和第二逻辑部分。非易失性存储器包括：电压检测器，被配置为检测外部提供给非易失性存储器和控制器单元的电源电压，并且将检测的输出提供给设置有电压检测器的非易失性存储器的第一逻辑部分，并且还同时通过缓冲放大器将控制器单元的第二逻辑部分和/或至少一个相加的非易失性存储器的逻辑部分。

6. 发明授权

US07744006B2 Semiconductor device and memory card having the same 有权
标题翻译：半导体装置和存储卡具有相同的功能
公开(公告)号：US07744006B2
公开(公告)日：2010-06-29
申请号：US12115418
申请日：2008-05-05
申请人： Nobuyoshi Nara
发明人： Nobuyoshi Nara
IPC分类号： G06K19/05
CPC分类号： G06K19/07
摘要： A semiconductor device includes a first circuit which operates in accordance with an internal clock, a second circuit which generates information of which an external apparatus is to be notified, an interface section which notifies the external apparatus of the information generated by the second circuit without using the first circuit upon receiving a predetermined command from the external apparatus, and a plurality of terminals each of which is connectable to one of power terminals and ground terminals provided on a substrate. The information is determined depending on whether each of the plurality of terminals is electrically connected to the power terminal or ground terminal on the substrate.
摘要翻译：半导体器件包括：根据内部时钟进行工作的第一电路，产生要通知外部设备的信息的第二电路;接口部，其向外部设备通知由第二电路生成的信息，而不使用所述第一电路在从外部设备接收到预定命令时，以及多个端子，每个端子可连接到设置在基板上的电源端子和接地端子中的一个。信息取决于多个端子中的每一个是否电连接到基板上的电源端子或接地端子。

7. 发明授权

US07370810B2 Semiconductor device and memory card having the same 有权
标题翻译：半导体装置和存储卡具有相同的功能
公开(公告)号：US07370810B2
公开(公告)日：2008-05-13
申请号：US11513025
申请日：2006-08-31
申请人： Nobuyoshi Nara
发明人： Nobuyoshi Nara
IPC分类号： G06K19/05
CPC分类号： G06K19/07
摘要： A semiconductor device includes a first circuit which operates in accordance with an internal clock, a second circuit which generates information of which an external apparatus is to be notified, an interface section which notifies the external apparatus of the information generated by the second circuit without using the first circuit upon receiving a predetermined command from the external apparatus, and a plurality of terminals each of which is connectable to one of power terminals and ground terminals provided on a substrate. The information is determined depending on whether each of the plurality of terminals is electrically connected to the power terminal or ground terminal on the substrate.
摘要翻译：半导体器件包括：根据内部时钟进行工作的第一电路，产生要通知外部设备的信息的第二电路;接口部，其向外部设备通知由第二电路生成的信息，而不使用所述第一电路在从外部设备接收到预定命令时，以及多个端子，每个端子可连接到设置在基板上的电源端子和接地端子之一。信息取决于多个端子中的每一个是否电连接到基板上的电源端子或接地端子。

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