专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07085982B2 Pulse generation circuit and semiconductor tester that uses the pulse generation circuit 有权
标题翻译：脉冲发生电路和采用脉冲发生电路的半导体测试仪
公开(公告)号：US07085982B2
公开(公告)日：2006-08-01
申请号：US10345230
申请日：2003-01-16
申请人： Kenichi Shinbo , Fujio Oonishi , Ritsurou Orihashi , Masashi Fukuzaki , Nobuo Motoki
发明人： Kenichi Shinbo , Fujio Oonishi , Ritsurou Orihashi , Masashi Fukuzaki , Nobuo Motoki
IPC分类号： G06F11/00 , G01R31/28
CPC分类号： G01R31/31922 , H03K5/135
摘要： A pulse generation circuit including a pulse formation circuit for generating normal and dummy pulses according to second delay value data, a data calculation circuit for calculating first delay value data at a timing at which the pulses are generated from the pulse formation circuit according to pattern data having information for determining whether to generate pulses from the pulse formation circuit, a dummy pulse control circuit for controlling generation of a dummy pulse in a no-pulse-generation cycle from the pulse formation circuit according to the second delay value data obtained by detecting the no-pulse-generation cycle from the first delay value data, and a logical gate circuit for eliminating the dummy pulses generated from the pulse formation circuit.
摘要翻译：一种脉冲发生电路，包括根据第二延迟值数据产生正常和虚拟脉冲的脉冲形成电路，数据计算电路，用于根据图形数据从脉冲形成电路产生脉冲的定时计算第一延迟值数据具有用于确定是否从脉冲形成电路产生脉冲的信息;虚拟脉冲控制电路，用于根据通过检测所述脉冲发生电路获得的第二延迟值数据从脉冲形成电路控制无脉冲生成周期中的伪脉冲的产生来自第一延迟值数据的无脉冲生成周期，以及用于消除从脉冲形成电路产生的伪脉冲的逻辑门电路。

2. 发明授权

US06768953B2 Test apparatus 有权
公开(公告)号：US06768953B2
公开(公告)日：2004-07-27
申请号：US10269380
申请日：2002-10-10
申请人： Fujio Oonishi , Kenichi Shinbo , Ritsuro Orihashi , Masashi Fukuzaki , Nobuo Motoki
发明人： Fujio Oonishi , Kenichi Shinbo , Ritsuro Orihashi , Masashi Fukuzaki , Nobuo Motoki
IPC分类号： G01R2926
CPC分类号： G01R31/3193
摘要： In an odd side storage circuit, logical values of a decision subject signal HCMP are stored in first and second FFs respectively at decision edges LH and HL generated from odd-numbered edges of a decision edge EH. Logical values of a delayed decision subject signal HCMP′ are stored in third and fourth FFs. According to a selection signal generated by a selection signal generation circuit based on outputs of the third and fourth FFs, a first selector selects an output of the first or second FF. An even side storage circuit operates similarly at even-numbered edges. A second selector selects the odd and even side storage circuits alternately. The FFs in the odd and even side storage circuits are reset by a decision edge LH′ of the even side and the decision edge HL of the odd side, respectively.

3. 发明授权

US06697755B2 Test apparatus 有权
标题翻译：测试仪器
公开(公告)号：US06697755B2
公开(公告)日：2004-02-24
申请号：US10159146
申请日：2002-05-31
申请人： Fujio Oonishi , Kenichi Shinbo , Ritsuro Orihashi , Masashi Fukuzaki , Nobuo Motoki
发明人： Fujio Oonishi , Kenichi Shinbo , Ritsuro Orihashi , Masashi Fukuzaki , Nobuo Motoki
IPC分类号： G01D1800
CPC分类号： G01R31/3193
摘要： In an odd side storage circuit, logical values of a decision subject signal HCMP are stored in first and second FFs respectively at decision edges LH and HL generated from odd-numbered edges of a decision edge EH. Logical values of a delayed decision subject signal HCMP′ are stored in third and fourth FFs. According to a selection signal generated by a selection signal generation circuit based on outputs of the third and fourth FFs, a first selector selects an output of the first or second FF. An even side storage circuit operates similarly at even-numbered edges. A second selector selects the odd and even side storage circuits alternately. The FFs in the odd and even side storage circuits are reset by a decision edge LH′ of the even side and the decision edge HL of the odd side, respectively.
摘要翻译：在奇数侧存储电路中，决策对象信号HCMP的逻辑值分别存储在从判定边缘EH的奇数边缘产生的判定边缘LH和HL处的第一和第二FF中。延迟决定对象信号HCMP'的逻辑值存储在第三和第四FF中。根据由选择信号发生电路基于第三和第四FF的输出产生的选择信号，第一选择器选择第一或第二FF的输出。偶数侧存储电路在偶数边缘类似地工作。第二选择器交替地选择奇数和偶数侧存储电路。奇数侧和偶数侧存储电路中的FF分别由奇数侧的判定边缘LH'和奇数侧的判定边缘HL复位。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式